3,801 technical terms and definitions
safety island chip design, hardware diagnostic coverage, safe state machine design, fmeda analysis
ISO 26262 functional safety for an automotive SoC connects vehicle hazards to goals, requirements, architecture, verification, and production controls. An Automotive Safety…
lithography
Iso-Dense Bias is a systematic CD difference between isolated features and dense periodic arrays patterned from identical mask dimensions, arising from optical proximity effects…
packaging
J-lead is the curved inward lead style where terminals wrap under the package body in a J-like profile - it reduces package footprint while maintaining leaded electrical…
japan chip revival, what is japan chip revival
An umbrella term for renewed semiconductor investment. Japan chip revival describes efforts to strengthen semiconductor manufacturing, research, design support, and supply-chain…
DRAM dominance, manufacturing excellence, US-Japan competition, memory market, semiconductor trade
The Japanese semiconductor industry is the collection of companies and coordinated national efforts that made Japan a dominant force in chip manufacturing, especially in memory…
Jay W. Lathrop, James Nall, Lathrop and Nall, Diamond Ordnance Fuze Laboratories, inverted microscope lithography, 1957 photolithography invention
Jay W. Lathrop was an American engineer who, together with James R. Nall, invented photolithography for semiconductor devices at the US Army's Diamond Ordnance Fuze Laboratories…
jedec, standards
JEDEC standards for packaging is the industry specifications from JEDEC that define package handling, reliability testing, dimensions, and moisture controls - they provide common…
ieee 1149.1 boundary scan, tap controller debug, on-chip debug trace, jtag test access port
Design-for-test architectures, automatic test pattern generation, and structural fault modeling constitute the digital verification and manufacturing test disciplines engineered…
junction transistor device process flow, alloy junction transistor process, grown junction transistor process, alloy-junction transistor fabrication, indium alloy regrowth germanium, base width furnace control
Junction Transistor Device Process Flow: Alloy Regrowth, Eutectic Doping & Furnace-Controlled Base Width The junction transistor replaced a human hand with a furnace. Where…
alloy junction wafer lapping, wafer lapping punch through margin, alloy junction base width series resistance, wafer total thickness variation TTV
Junction Transistor Wafer Lapping: The Punch-Through Floor and the Series-Resistance Ceiling Wafer lapping is the first step in the alloy-junction process flow, and it sets…
junctionless fet fabrication, junctionless vs inversion mode, junctionless doping profile, junctionless process simplification
Junctionless Transistors: Device Physics, Full Depletion Limits & Monolithic 3D In classical inversion-mode MOSFETs (FinFETs and Gate-All-Around nanosheets), current modulation…
high-k anneal, post deposition anneal, hkmg thermal treatment, eot stabilization, hkmg
High-k metal gate (HKMG) integration, replacement metal gate (RMG / gate-last) processing, and dual work function metal (WFM) engineering constitute the foundational materials…
k-means clustering wafer map pattern prediction, k-means clustering wafer, clustering wafer map, wafer map pattern, map pattern prediction, k-means clustering, wafer map
K-Means Clustering Wafer Map Pattern Prediction with Machine Learning Introduction & Motivation K-Means Clustering Wafer Map Pattern Prediction with Machine Learning addresses…
rayleigh equation, resolution enhancement, process difficulty, lithography k1, multi-patterning
The k1 factor is the single number in the Rayleigh resolution equation that measures how hard a lithography process is being pushed relative to the physical limit of its own…
metrology
Kelvin Contact (Four-Terminal Sensing) is the precision resistance measurement technique that eliminates probe contact resistance and lead resistance errors by using separate…
metrology
A Kelvin probe measures contact potential difference (CPD)—the electrostatic potential between a vibrating probe tip and a sample surface—via an AC capacitive coupling…
kelvin probe force microscopy, kpfm, metrology
Kelvin Probe Force Microscopy (KPFM) is a scanning probe technique that measures the local contact potential difference (CPD) between a conductive AFM tip and a sample surface…
wafer dicing, scribe street width, blade dicing, laser dicing, plasma dicing, die per wafer, singulation
Kerf loss is the silicon area destroyed, not just divided, when a wafer gets cut into individual die — the width of material the saw blade, laser, or plasma stream actually…
metrology
Killer defect size is the minimum defect dimension that causes device failure — a critical threshold that determines inspection sensitivity requirements, with smaller nodes…
kgd, advanced packaging
Known Good Die (KGD) is a semiconductor die that has been fully tested and verified to be functional before being assembled into a multi-die package — ensuring that only working…
anisotropic silicon etching, wet etch silicon, potassium hydroxide etch, mems bulk micromachining, crystal plane etch, koh silicon etch, crystallographic etch, v groove etch
KOH etching is crystal-programmed silicon machining: hydroxide chemistry supplies removal, but wafer orientation, mask azimuth, plane-rate ratios, corner evolution…
South Korea semiconductors, DRAM and flash leadership, conglomerate investment, memory cycles, shifting memory leadership
The Korean memory industry is the collection of South Korean companies and national efforts that made South Korea a dominant force in semiconductor memory, rising after Japan…
krf, krypton fluoride, lithography
KrF (krypton fluoride) excimer lasers produce 248nm deep-UV light, and were the industry's workhorse exposure source from roughly 1996 to 2005 — carrying the transition…
krf lithography, what is krf lithography
KrF lithography uses krypton-fluoride excimer-laser light to expose photoresist. Its nominal wavelength is 248 nanometers, within deep ultraviolet. The laser is part of a larger…
lab-on-chip integration
Lab-On-Chip Integration Introduction & Motivation Lab-On-Chip Integration addresses a central problem in microfluidics process control and device-footprint-mm2 prediction: how…
lab on chip reagent dispense accuracy prediction with machine learning, lab chip reagent dispense accuracy prediction machine learning, lab chip, lab-on-chip reagent
Lab-on-Chip Reagent Dispense Accuracy Prediction with Machine Learning Introduction & Motivation Lab-on-Chip Reagent Dispense Accuracy Prediction with Machine Learning addresses…
analytical lagrangian dynamics, euler lagrange mechanics, generalized coordinate mechanics, variational mechanics, lagrangian mechanics semiconductor, engineering lagrangian modeling
Lagrangian mechanics predicts motion by expressing a system through generalized coordinates, kinetic and potential structure, constraints, and generalized forces. Instead…
metrology
Lamella preparation is the process of creating an ultra-thin specimen slice (<100 nm thick) from a specific location in a semiconductor device for examination in a Transmission…
lga, packaging
Land grid array is the array package type that uses flat metal lands instead of solder balls on the package bottom - it supports fine-pitch high-I O interfaces with socketed…
metrology
A Langmuir probe is a physical diagnostic tool inserted directly into a plasma to measure fundamental plasma parameters: electron density, electron temperature, plasma potential…
wafer lapping, double-sided lapping, lapping slurry, subsurface damage, sawing damage, alumina grit, silicon carbide grit
Lapping is the wafer-preparation step in which a sliced semiconductor disc is rubbed between two flat plates with a loose abrasive slurry, removing the rough, cracked surface left…
metrology
Laser Ablation ICP-MS (LA-ICP-MS) is an analytical technique that combines pulsed laser ablation of a solid sample with inductively coupled plasma mass spectrometric detection…
laser bonding chiplet, localized laser reflow, fine pitch microbump laser attach, selective laser solder reflow
Laser-assisted bonding heats only the bond site itself, a localized spot measured in microseconds, instead of putting the whole package through a furnace cycle the way…
advanced packaging
Laser Debonding is a non-contact wafer separation technique that uses a focused laser beam to ablate the adhesive layer at the carrier-wafer interface — scanning through…
laser dicing debris redeposition prediction machine learning, laser dicing, debris redeposition prediction, laser dicing debris redeposition prediction, laser dicing debris
Laser Dicing Debris Redeposition Prediction with Machine Learning Introduction & Motivation Laser Dicing Debris Redeposition Prediction with Machine Learning addresses a central…
metrology
Laser interferometer is a precision measurement instrument that uses the interference of laser light waves to measure distances, displacements, and velocities with sub-nanometer…
packaging
Laser marking is the package-identification process that uses focused laser energy to permanently mark codes, logos, and traceability data on component surfaces - it provides…
lithography, DUV laser, SLM, spatial light modulator, gray-scale lithography, display photomask, MEMS mask, mature node masks, mask write cost
A laser mask writer patterns a mask blank using focused laser light instead of an electron beam — trading away the fine resolution VSB e-beam delivers in exchange for dramatically…
lithography
Photomask fabrication, phase-shift mask engineering, and nanoscopic defect repair constitute the foundational master-patterning technologies that enable optical projection…
stealth dicing wafer, internal laser modified layer silicon, kerf less wafer singulation
Laser Stealth Dicing Cutting a finished wafer into individual dies used to mean dragging a diamond-coated blade or a plasma etch straight through the silicon along the scribe…
laser wafer marking readability prediction, laser wafer marking, wafer marking readability, marking readability prediction, laser wafer, wafer marking, marking readability
Laser Wafer Marking Readability Prediction with Machine Learning Introduction & Motivation Laser Wafer Marking Readability Prediction with Machine Learning addresses a central…
prefetching parallel, computation communication overlap, pipelining latency, double buffering
Latency Hiding is the parallel computing technique of overlapping computation with data movement (memory loads, network communication, disk I/O) so that the processor is never…
advanced packaging
Layer Transfer is the process of detaching a thin crystalline semiconductor layer from its original substrate and bonding it onto a different substrate — enabling the combination…
physical design, place and route flow, chip layout, ic layout, custom layout, pnr flow
Layout design is the physical-design discipline of transforming a logical circuit netlist into geometric shapes on silicon — assigning every transistor, standard cell, wire…
IC layout, physical design, mask layout, polygon editing, chip geometry, layout tool
A layout editor is the software tool used to create and manipulate the physical geometry of an integrated circuit — the actual shapes on each layer that define where transistors…
liquid-crystal display driver, display controller, segment driver, multiplexed display, display interface chip
An LCD driver is a specialized integrated circuit that generates the electrical signals needed to control a liquid-crystal display, translating the digital data of what should…
semiconductor leadframe, QFN lead frame, QFP lead frame, die paddle, lead frame package
Lead frame. is a stamped or chemically etched metal skeleton that supports a semiconductor die and forms electrical leads in molded packages such as QFN, QFP, SO, and many power…
packaging
Lead-free package requirements is the set of material, thermal, and reliability conditions that package designs must satisfy for lead-free assembly environments - they ensure…
packaging
Lead-free solder (and the associated lead-free soldering process) refers to the class of non-toxic, environmentally compliant metallic alloy systems formulated without intentional…
packaging
Lead pitch is the center-to-center spacing between adjacent package leads or terminals - it determines PCB footprint density, assembly capability, and inspection complexity. What…