215 technical terms and definitions
first principles simulation, density functional theory, quantum materials modeling, electronic structure calculation, dft semiconductor
Etch Plasma–Surface Ab Initio Molecular Dynamics (AIMD) Modeling follows atomic trajectories while recomputing electronic-structure forces from first principles at every time…
metrology
Aberration-Corrected TEM is a TEM equipped with hardware correctors (multipole lens systems) that eliminate spherical and chromatic aberrations — pushing the resolution limit…
metrology
Accuracy, as a model evaluation metric, is simply the fraction of predictions a model got right — correct predictions divided by total predictions. It's the most intuitive metric…
interposer, chiplet, integration, routing
Active Interposer Design Integration is a silicon substrate containing embedded logic, routing resources, and power management circuits that actively orchestrates communication…
adaptive metrology sampling plan optimization machine learning, adaptive metrology, sampling plan optimization, adaptive metrology sampling plan optimization
Adaptive Metrology Sampling Plan Optimization with Machine Learning Introduction & Motivation Adaptive Metrology Sampling Plan Optimization with Machine Learning addresses…
advanced packaging
Adhesive Bonding is a wafer-level bonding technique that uses polymer adhesive layers to join two substrates — offering the lowest bonding temperature (< 200°C), highest…
dram capacitor technology, dram cell architecture, high k dram capacitor, dram buried wordline
High-bandwidth memory (HBM) is DRAM stacked vertically and connected to its host through an interface thousands of bits wide, running beside the processor on an interposer rather…
aib, advanced packaging
Advanced Interface Bus (AIB) is an open-source die-to-die interconnect standard originally developed by Intel and released under the DARPA CHIPS program — providing a parallel…
193nm immersion lithography, immersion scanner resolution, pellicle lithography, lithography overlay
193nm Immersion Lithography is the workhorse patterning technology that has defined semiconductor manufacturing from the 45nm node through today's most advanced EUV-assisted nodes…
photomask fabrication process, mask blank defect, pellicle euv mask, reticle enhancement technique
Photomask fabrication, phase-shift mask engineering, and nanoscopic defect repair constitute the foundational master-patterning technologies that enable optical projection…
CD-SEM, scatterometry, OCD, critical dimension measurement
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…
semiconductor mathematics, lithography mathematics, computational physics, numerical methods
Advanced Mathematics in Semiconductor Manufacturing 1. Lithography & Optical Physics This is arguably the most mathematically demanding area of semiconductor manufacturing. 1.1…
3d integration, chiplet, chiplets, cowos, hybrid bonding, microbump, tsv, hbm, hbm3e, hbm4, interposer, rdl, tcb, besi, disco, ucie, 2.5d packaging, heterogeneous integration, book 5
Advanced Packaging & 3D Integration: Beyond Moore's Law When the economic and physical scaling of photolithography hit the reticle-size limit ( ), the semiconductor industry…
chiplet heterogeneous integration, 2.5D interposer packaging, fan-out wafer level packaging, cowos
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
advanced packaging and chiplet economics, advanced packaging chiplet, packaging chiplet economics, advanced packaging, packaging chiplet, chiplet economics
Advanced Packaging and Chiplet Economics Introduction & Motivation Advanced Packaging and Chiplet Economics addresses a central problem in manufacturing process control…
cowos info package platforms, 2.5d 3d hbm stacking, ucie die interconnect standard, hybrid bonding package substrate, cowos
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
chip on wafer on substrate, hbm integration cowos, tsmc cowos s l r, silicon interposer packaging
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
heterogeneous integration methods, chiplets
Advanced packaging is the set of technologies that connect, protect and cool silicon after it leaves the fab. It has moved from a cost-driven back-end afterthought to a primary…
fcbga, flip chip bga, abf substrate, coreless substrate, organic interposer packaging
Advanced Packaging Substrates are the organic multilayer circuit boards that mechanically support and electrically connect packaged ICs to printed circuit boards — serving as…
advanced packaging yield reliability prediction machine learning, advanced packaging, yield reliability prediction, csam, advanced packaging yield, packaging yield
Advanced Packaging Yield and Reliability Prediction with Machine Learning Introduction & Motivation Advanced Packaging Yield and Reliability Prediction with Machine Learning…
apc semiconductor, run to run control, feedback feedforward process, fab automation control
Advanced process control (APC) uses measurements, process models, and qualified adjustments to keep semiconductor manufacturing outputs near their targets. Instead of using…
apc semiconductor, run to run control, feedback feedforward process, fab automation control, r2r control, ewma controller, ewma run to run control, metrology delay, apc framework, run to run control tuning, semi e133
Advanced process control is the layer of a fab that chooses what recipe the next lot will run, using what the last lot measured. It is not statistical process control, which…
source mask optimization, smo lithography, full chip smo, inverse lithography technology, opc
Computational Lithography and Optical Proximity Correction constitute the mathematical and algorithmic backbone of sub-wavelength semiconductor patterning. Operating deep within…
semiconductor packaging advanced, fan out wafer level, chiplet packaging
For most of computing history, more performance meant more transistors on one monolithic die. As that path slows, the industry increasingly gains performance through advanced…
advanced packaging predicting layer-to-layer registration accuracy in multilayer substrates using process parameters, advanced packaging predicting, packaging predicting layer-to-layer
Advanced Packaging: Predicting layer-to-layer registration accuracy in multilayer substrates using process parameters Introduction & Motivation Advanced Packaging: Predicting…
organic substrate scaling, glass core substrate, high density redistribution, substrate signal integrity, power delivery network, AI accelerator packaging, fine pitch routing, redistribution layer, substrate warpage
Advanced substrate technology is the next generation of package substrate platforms — built with finer routing lines and improved dielectric materials — that increase signal…
advanced mathematics, semiconductor mathematics, lithography math, plasma physics, diffusion math
Semiconductor Manufacturing: Advanced Mathematics 1. Lithography & Optical Physics This is arguably the most mathematically demanding area of semiconductor manufacturing. 1.1…
lithography
Aerial Image Inspection is a mask inspection technique that evaluates the mask based on the image it will actually produce in the lithographic exposure system — rather than…
defense, semiconductor, avionics, military, specification, mil, reliability
Aerospace Defense Semiconductor is military-grade semiconductor components for aircraft, missiles, defense systems meeting strict specifications for reliability, radiation…
afm profilometry, atomic force microscopy, atomic force microscope, afm metrology, metrology
Atomic force microscopy profiles a surface by rastering a sharp tip on a flexible cantilever and using a feedback-controlled z scanner to follow the tip-sample interaction.…
atomic force profilometry, contact mode afm, tapping mode afm, cd-afm, kelvin probe force microscopy, scanning capacitance microscopy, scm semiconductor
Atomic force microscopy profiles a surface by rastering a sharp tip on a flexible cantilever and using a feedback-controlled z scanner to follow the tip-sample interaction.…
metrology predicting afm calibration drift in surface roughness measurements, metrology predicting afm, predicting afm calibration, afm calibration drift, calibration drift surface
Metrology: Predicting AFM calibration drift in surface roughness measurements Introduction & Motivation Metrology: Predicting AFM calibration drift in surface roughness…
ml chip floorplan, automated macro placement, neural network floorplan optimization, reinforcement learning floorplanning
AI-Driven Floorplanning is the automated placement of large blocks and macros on chip floorplan using reinforcement learning and graph neural networks — where RL agents learn…
inference accelerator, inference asic, production ai serving chip
AI inference chip definition and engineering boundary. is hardware optimized to execute trained neural networks under production latency, throughput, energy, and cost constraints.…
aims, lithography
AIMS (Aerial Image Measurement System) is a dedicated metrology tool that emulates the optical conditions of a lithographic scanner to image mask features — reproducing the exact…
metrology
Air bearing table is an ultra-stable measurement platform that floats on a thin film of compressed air — providing friction-free, vibration-isolated support for sensitive…
ald kinetics, atomic layer deposition kinetics, ald growth per cycle, atomic layer deposition, ald, ald (atomic layer deposition), atomic layer deposition process, thermal ald, plasma-enhanced ald, peald, spatial ald, thin film ald
Atomic layer deposition is a vapor-phase thin-film deposition technique that builds material one atomic layer at a time through sequential, self-limiting chemical reactions…
ald kinetics, atomic layer deposition kinetics, ald growth per cycle, ald barrier, tantalum nitride barrier, tan ald, diffusion barrier interconnect, copper barrier layer, ald
Atomic Layer Deposition is the vapor-phase thin film synthesis technique based on sequential, self-limiting gas-surface chemical reactions that achieves digital monolayer…
ald kinetics, atomic layer deposition kinetics, ald growth per cycle, ald cobalt, cobalt atomic layer deposition, cobalt seed layer, cobalt liner, co ald interconnect, ald
Atomic Layer Deposition is the vapor-phase thin film synthesis technique based on sequential, self-limiting gas-surface chemical reactions that achieves digital monolayer…
ald kinetics, atomic layer deposition kinetics, ald growth per cycle, ald cycle, atomic layer deposition cycle, ald half cycle, ald pulse purge cycle, ald cycle timing, ald saturation curve, precursor pulse purge, ald exposure dose
An atomic layer deposition (ALD) cycle is a deliberately separated sequence of surface reactions: precursor A exposure, purge or evacuation, reactant B exposure, and a second…
ald kinetics, atomic layer deposition kinetics, ald growth per cycle, ald precursor chemistry, atomic layer deposition mechanism, ald nucleation, ald self limiting reaction, thermal ald plasma ald, ald
Atomic Layer Deposition is the vapor-phase thin film synthesis technique based on sequential, self-limiting gas-surface chemical reactions that achieves digital monolayer…
atomic layer deposition, ald, ald basics, atomic layer deposition process, thin film deposition ald, high conformality ald, ald cycle
Atomic layer deposition is a vapor-phase thin-film deposition technique that builds material one atomic layer at a time through sequential, self-limiting chemical reactions…
ald kinetics, atomic layer deposition kinetics, ald growth per cycle, ALD process optimization, atomic layer deposition chemistry, ALD precursor, ALD window, ald
Atomic Layer Deposition is the vapor-phase thin film synthesis technique based on sequential, self-limiting gas-surface chemical reactions that achieves digital monolayer…
overlay metrology 3d, alignment mark design, ir alignment through silicon, alignment error budget
Alignment Accuracy Requirements in 3D Integration: Metrology, Physics & Error Budgets In 3D semiconductor integration, alignment accuracy defines the spatial precision with which…
lithography
Alignment marks are dedicated reference patterns etched or built onto the wafer whose sole purpose is to give every subsequent lithography step a fixed, measurable coordinate…
alloy junction 1952 crystal integrity device fabrication, thermal stress induced dislocation cracking, four point probe resistivity profile ingot
Cool and Inspect the Crystal: Where Step Three's Tolerance Band Gets Measured, Not Assumed Step three managed a drift it could only anticipate; this step is the first point in…
alloy junction 1952 support thin germanium piece assembly, flexural rigidity thin plate deflection wafer, fixture contact stress concentration fracture
Load the Positioning Fixture: Where Step Six's Thickness Choice Becomes a Handling Risk Step six's thickness choice was framed as a trade between wafer count and fragility — more…
alloy junction 1952 remove surface material bridging junction boundaries, parasitic surface bridge parallel resistance junction, restore reverse junction resistance post alloy etch
Perform Post-Alloy Etching: Breaking a Parasitic Bridge, Not Cleaning a Surface It would be easy to mistake this step for Step 8's cleanup etch happening a second time, later…
alloy junction 1952 prevent contamination from tab or attachment materials, galvanic couple nickel germanium etch bath, faraday law galvanic etch depth contribution
Protect the Base Attachment During Etching: A Second Metal Changes the Chemistry Step 30's etch rate law, , assumed a single material sitting in the bath: germanium, dissolving…
alloy junction 1952 multi cycle fresh water rinse after etching, diffusion limited clearance of trapped rinse contaminant, geometric decay residual contamination rinse cycles
Rinse and Dry Thoroughly: Why "Thoroughly" Means Repeated, Not Longer Step 9's rinse, back in Phase 1, was clearing loose particulate off a bare slice with no electrical stakes…