known good die for chiplets

Known Good Die (KGD) is a semiconductor die that has been fully tested and verified to be functional before being assembled into a multi-die package — ensuring that only working chiplets are integrated into expensive 2.5D/3D packages where replacing a defective die after assembly is impossible, making KGD testing the critical yield gatekeeper that determines the economic viability of chiplet-based architectures.

What Is KGD?

• Definition: A bare die (unpackaged chip) that has undergone sufficient electrical testing, burn-in, and screening to guarantee it will function correctly when assembled into a multi-chip module (MCM), 2.5D interposer package, or 3D stacked package — the "known good" designation means the die has been tested to the same confidence level as a packaged chip.
• Why KGD Is Hard: Testing a bare die is fundamentally more difficult than testing a packaged chip — bare dies have tiny bump pads (40-100 μm pitch) that require specialized probe cards, the die is fragile without package protection, and some tests (high-speed I/O, thermal) are difficult to perform on unpackaged silicon.
• Test Coverage Gap: Traditional wafer probe testing achieves 80-90% fault coverage — sufficient for single-die packages where final test catches remaining defects, but insufficient for multi-die packages where a defective die wastes all other good dies in the package.
• KGD Requirement: Multi-die packages need >99% KGD quality — if 4 chiplets each have 99% KGD quality, package yield from die quality alone is 0.99⁴ = 96%. At 95% KGD quality, package yield drops to 0.95⁴ = 81%, wasting 19% of expensive assembled packages.

Why KGD Matters

• Yield Economics: In a multi-die package costing $1000-5000 to assemble, incorporating one defective die wastes the entire package plus all other good dies — KGD testing cost ($5-50 per die) is trivial compared to the cost of a scrapped package.
• No Rework: Unlike PCB assembly where a defective chip can be desoldered and replaced, multi-die packages with underfill and molding compound cannot be reworked — a defective chiplet means the entire package is scrapped.
• Chiplet Architecture Enabler: The economic case for chiplets depends on KGD — splitting a large die into 4 chiplets only improves yield if each chiplet can be verified good before assembly, otherwise the yield advantage of smaller dies is lost during integration.
• HBM Quality: HBM memory stacks contain 8-12 DRAM dies — each die must be KGD tested before stacking, as a single defective die in the stack renders the entire HBM stack (and potentially the GPU package) defective.

KGD Testing Methods

• Wafer-Level Probe: Standard probe testing at wafer level using cantilever or MEMS probe cards — tests digital logic, memory BIST, analog parameters at 40-100 μm pad pitch.
• Wafer-Level Burn-In (WLBI): Accelerated stress testing at elevated temperature (125-150°C) and voltage (1.1× nominal) on the wafer — screens infant mortality failures that would escape room-temperature probe testing.
• Known Good Stack (KGS): For 3D stacking, each partial stack is tested before adding the next die — a 4-die HBM stack is tested at 1-die, 2-die, and 3-die stages to catch failures early.
• Redundancy and Repair: Memory dies (HBM, DRAM) include redundant rows/columns that can replace defective elements — repair is performed during KGD testing, improving effective die yield.

KGD is the quality foundation that makes multi-die packaging economically viable — providing the pre-assembly testing and screening that ensures only functional chiplets enter the expensive integration process, with KGD quality directly determining whether chiplet-based architectures achieve their promised yield and cost advantages over monolithic designs.