29,258 technical terms and definitions
wafer edge trim, edge bead removal, particle contamination control, edge film flaking
The bevel etch is the first step in this entire project that targets a region of the wafer that was never going to become part of a working device at all, and it runs not once…
BLC, direct contact DC etch, self aligned contact DRAM, silicon over-recess, contact resistance DRAM
The bitline contact — called BLC or DC (Direct Contact) depending on the maker — etches straight down through nitride and oxide into the exact center of an active area with no…
BL etch, GBL etch, multi-material conductor etch, tungsten polysilicon etch, bitline gate integration
The bitline stack etch — BL Etch or GBL Etch — cuts straight down through a tall sandwich of materials in one continuous pass: a SiN cap on top, then tungsten, then a TiN or WSi…
bitline cap trim etch, SiN cap height correction, secondary trim DRAM, CD correction budget
The BL cap trim is a secondary, targeted etch applied to the SiN cap sitting on top of the bitline stack after the main stack etch has already finished, adjusting that cap's final…
nitride oxide nitride spacer, N O N multilayer spacer, storage node contact self alignment, bitline parasitic capacitance
The bitline spacer etch forms a multilayer nitride-oxide-nitride sidewall around the finished bitline conductor stack, and it is a genuinely different problem from…
redistribution layer etch, rdl fan out pitch, bump pitch hbm, bump site open etch
Every metal layer covered earlier in this project connects two adjacent structures that already sit at roughly the same pitch regime; the redistribution layer exists for…
vct buried bitline, vertical channel dram bitline, buried bitline integration, emerging dram architecture bitline
The buried bitline trench exists specifically because the vertical channel pillar covered in the previous round freed up a physical level that a horizontal cell's bitline could…
buried word line DRAM, BWL DRAM, recessed channel array transistor, RCAT DRAM, saddle-fin DRAM transistor, GIDL DRAM word line, word line GIDL, sub word line driver, hierarchical word line, DRAM Vpp word line boost
DRAM Buried Word Line: Saddle-Fin Gate Architecture, the GIDL Trade-Off, and Hierarchical Row Activation A buried word line (BWL) is a DRAM access-transistor gate that no longer…
BWL etch, WL trench, gate trench DRAM, saddle fin recess, GIDL control, BCAT transistor
The buried wordline trench etch — called BWL Etch, WL Trench, or Gate Trench depending on the maker — carves the channel for a DRAM access transistor's gate down into the silicon…
dram capacitor aspect ratio uniformity prediction, dram capacitor aspect, capacitor aspect ratio, aspect ratio uniformity, ratio uniformity prediction, aspect ratio
DRAM Capacitor Aspect Ratio Uniformity Prediction with Machine Learning Introduction & Motivation DRAM Capacitor Aspect Ratio Uniformity Prediction with Machine Learning addresses…
dram capacitor contact etch, plate contact etch, PC etch dram, dram pc via, capacitor plate bias via
The capacitor contact etch is the final via cut in the DRAM capacitor module, the step that drills down from the periphery metal level to reach the shared top electrode plate so…
dram capacitor dielectric leakage current prediction, dram capacitor dielectric, capacitor dielectric leakage, dielectric leakage current, dram capacitor
DRAM Capacitor Dielectric Leakage Current Prediction with Machine Learning Introduction & Motivation DRAM Capacitor Dielectric Leakage Current Prediction with Machine Learning…
dram capacitor leakage drift prediction, dram capacitor leakage, capacitor leakage drift, leakage drift prediction, dram capacitor, capacitor leakage, leakage drift, drift prediction
DRAM Capacitor Leakage Drift Prediction with Machine Learning Introduction & Motivation DRAM Capacitor Leakage Drift Prediction with Machine Learning addresses a central problem…
DRAM cell, what is a DRAM cell, 1T1C cell, dynamic RAM, DRAM refresh, destructive read
A DRAM cell, short for dynamic random-access memory cell, is the basic one-bit memory building block made from just a single transistor and a single capacitor — the capacitor…
shallow trench isolation DRAM, active area isolation, etch loading cell array, pad nitride strip, STI oxide recess
The cell STI etch cuts the shallow trench isolation that electrically separates one DRAM cell's active area from its neighbor, and inside the array this trench has to be narrower…
copper electroplating superfill, cmp dishing erosion, barrier seed layer, damascene cmp
The Cu damascene fill picks up exactly where the M1 trench and via etches left off: those etches only produced an empty mold, and this is the sequence of deposition and polishing…
M0C etch, deep contact DRAM, array to periphery contact, strap contact DRAM, high aspect ratio periphery contact
The deep MC contact — also called M0C or Deep Contact — has to etch all the way down through the entire height of the capacitor stack to reach the periphery transistors below it…
dram-device-architecture, dram device architecture, dram architecture, 1t1c dram cell architecture, buried wordline dram, dram capacitor scaling, dram array architecture
A DRAM device architecture is the hierarchical physical, structural, and electrical organization of Dynamic Random-Access Memory—spanning the unit one-transistor one-capacitor ( )…
ECC DRAM, SECDED, Hamming code DRAM, Chipkill, Advanced ECC, ECC DIMM, single error correction double error detection
DRAM ECC: Hamming SECDED Architecture, Reliability Theory, and the Chipkill Application ECC is the layer that stops pretending the physics underneath it is perfect. Every…
dram etch list, buried wordline etch, storage node hole etch, dram capacitor etch, dram process etch steps, 6f2 cell etch, bitline contact etch, mold dip out etch, hbm tsv etch
A modern 6F² buried-wordline DRAM cell runs through more than fifty named etch applications before a single bit can be stored, and nearly all of them exist to solve one problem…
dram cell structure, dram capacitor, dram refresh, 1t1c dram cell
DRAM (dynamic random-access memory) stores each bit as charge on a tiny capacitor, gated by a single access transistor — the '1T1C' cell. It is 'dynamic' because that charge leaks…
dram films
DRAM Film A DRAM film is a material layer used in the access transistor, storage capacitor or wiring of dynamic memory. Its role must be named: a capacitor dielectric and a gate…
dram film stack, dram film stacks
DRAM Filmstack A DRAM filmstack is an ordered set of layers belonging to a particular DRAM structure. There is no single stack covering the access transistor, capacitor, bit line…
dram front-end back-end integration, dram wafer to hbm packaging flow
DRAM front-end to back-end process integration is the single traveler that carries a bare silicon wafer through every module needed to make a working memory chip — cell…
laser fuse trim, electrical fuse dram, fuse repair dram, final test trim window
The fuse window etch is the first step in this entire project where the target is neither a clean clear-to-material opening nor a controlled-depth trench stopping partway through…
HM open, ACL open, amorphous carbon hard mask, DRAM cell module patterning, SADP mandrel
The hard-mask open — HM Open or ACL Open depending on the maker — etches a pattern into a sacrificial amorphous carbon, polysilicon, or silicon nitride layer so that layer can…
ACL strip, HM removal, amorphous carbon ash, dry ash wet strip, DRAM process cleanup
The hard-mask strip — ACL Strip or HM Removal depending on the maker — removes the amorphous carbon, poly, or nitride hard mask once it has finished protecting the real feature…
LP separation, LP isolation, tungsten TiN pad patterning, misalignment tolerant contact, SNC to capacitor bridge
The landing pad etch patterns a tungsten or TiN pad sitting directly above the storage node contact, deliberately sized larger than the SNC it connects to specifically so it can…
sige selective recess, isotropic sige undercut, channel release etch, nanosheet gap formation
The lateral SiGe recess demands exactly the opposite chemistry goal from the superlattice stack etch that immediately precedes it — where that round needed near-equal Si and SiGe…
chop etch, trim etch DRAM, active area cut, landing pad separation, DRAM island isolation
The line cut — also called chop etch or trim — takes the continuous parallel lines that self-aligned spacer patterning just produced and chops them into the separate, electrically…
LP gap recess, landing pad gap fill, nitride overburden recess, capacitor module surface prep
The LP gap fill etch-back recesses a nitride deposited into the gaps the landing pad separation etch just cut, and it exists for a reason specific to this module: a separation…
first metal trench, damascene trench etch dram, metal 1 interconnect etch, dual damascene dram
The M1 trench etch cuts a pattern of empty channels into the dielectric sitting directly above the contact layer, and those channels — not any metal — are the actual feature this…
core etch, SADP mandrel, SAQP self aligned quadruple patterning, sidewall spacer DRAM, mandrel pull
The mandrel etch, also called core etch, cuts the sacrificial core lines that self-aligned double and quadruple patterning build the rest of a DRAM array's dense pitch around…
FOX full oxide removal, HF LAL wet etch, free standing capacitor cylinders, sacrificial oxide removal timing
The mold dip-out is a timed wet etch, typically hydrofluoric acid or LAL (a buffered ammonium-fluoride mixture), that dissolves away the entire sacrificial oxide mold a wafer's…
capacitor hard mask, mask thickness budget, storage node hole etch prep, ACL poly mask capacitor
The mold hard-mask open patterns the poly or amorphous carbon layer that will stand in for photoresist through the storage node hole etch, and it has to be engineered to a far…
bottom electrode separation, BE etch back, TiN cut between cells, capacitor isolation etch, CMP vs dry etch back DRAM
Node separation, also called bottom electrode separation or BE etch-back, cuts the TiN bottom electrode layer between neighboring capacitor cylinders after the mold dip-out has…
pad oxide strip, hot phosphoric acid, H3PO4 wet strip, selective nitride removal, STI module cleanup
The pad nitride strip removes the silicon nitride layer that protected the active silicon all the way through the entire STI module — trench etch, fill, and oxide recess — using…
bond pad open, pad open etch dram, wire bond pad etch, sloped sidewall passivation
The passivation pad open etch demands exactly the opposite outcome from the fuse window etch covered in the previous round: complete, total clearance down to the bond pad metal…
dram peri gate spacer, sense amplifier transistor etch, dram logic transistor spacer, periphery gate etch
The peripheral gate spacer etch is the step that finally makes DRAM's support circuitry look like ordinary logic again, after six sections of exotic array-specific etching. Every…
dram peri sd contact, sense amp contact etch, io driver contact etch, rie lag dram
The peripheral source/drain contact etch cuts the via that lands on each peripheral transistor's source and drain regions, and it has to do that job across an enormous range…
BG bitline gate etch, high k metal gate DRAM, dual use integration, row decoder sense amp gate
The periphery gate etch, sometimes called BG or bitline-gate etch, is the same physical etch that forms the DRAM array's bitline stack, except run across the periphery region…
peri STI, row decoder isolation, sense amplifier isolation, etch loading periphery, shallow trench isolation periphery
Periphery STI is the same shallow trench isolation concept as cell STI, cut into the same wafer in the same process module, but wider and shallower because the periphery…
photosensitive polyimide, stress buffer coat, flip chip bump reliability, redistribution layer dram
The polyimide open is the final step in this entire DRAM etch sequence, and it closes the project with a genuine category question: many modern polyimide opens aren't a plasma…
fluorocarbon residue removal, oxygen plasma ash, wet amine strip, sidewall passivation byproduct
The post-etch polymer clean exists because of the exact mechanism that made the extreme aspect-ratio etches earlier in this project possible in the first place: the same…
dry clean dram, native oxide removal, siconi clean, cluster tool vacuum integration
The pre-clean etch runs a race against a chemical reaction that starts the instant it finishes, because the native oxide it removes from an exposed silicon or metal surface begins…
DRAM Process A DRAM process is the coordinated set of fabrication modules that makes memory cells and their peripheral circuits. For conventional one-transistor/one-capacitor…
DRAM Process Flow A DRAM process flow is the ordered integration plan linking transistor formation, contacts, capacitors, wiring and test. The diagram is a teaching sequence for…
refresh, bandwidth tradeoff, bank-level refresh, per-die refresh, HBM controller
DRAM Refresh-Bandwidth Tradeoff and Bank-Level Refresh Every DRAM cell loses charge over time and must be periodically read and rewritten to preserve its data, but a refresh…
dram refresh bitmap repair prediction, dram refresh bitmap, refresh bitmap repair, bitmap repair prediction, dram refresh, refresh bitmap, bitmap repair, repair prediction
DRAM Refresh Bitmap Repair Prediction with Machine Learning Introduction & Motivation DRAM Refresh Bitmap Repair Prediction with Machine Learning addresses a central problem…
dram refresh command overhead prediction, dram refresh command, refresh command overhead, command overhead prediction, dram refresh, refresh command, command overhead
DRAM Refresh Command Overhead Prediction with Machine Learning Introduction & Motivation DRAM Refresh Command Overhead Prediction with Machine Learning addresses a central problem…