peripheral source drain contact etch

The peripheral source/drain contact etch cuts the via that lands on each peripheral transistor's source and drain regions, and it has to do that job across an enormous range of contact sizes within the same etch step — something the array's rigidly uniform cell contacts never have to deal with. A sense amplifier's tiny differential-pair transistors need contacts barely larger than the gate spacer etch's own critical dimension, while an I/O driver pushing current on and off the chip's external pins needs contacts dozens of times wider to keep resistance low at high current, and both sit on the same periphery die area, patterned and etched in the same process step.

RIE lag — the well-known tendency of narrower openings to etch slower than wider ones in the same plasma step — turns this size diversity into a genuine process-window problem, not just a layout inconvenience. Because ion and radical transport into a narrow via is more restricted than into a wide one, a single fixed etch time that fully clears a wide I/O-driver contact can leave a narrow sense-amp contact under-etched, with residue still sitting at the bottom; foundries address this by tuning etch chemistry and overetch margin specifically against the smallest contact on the mask, accepting some additional overetch risk at the wide contacts in exchange for guaranteeing the narrow ones clear completely, since an incomplete small contact is the more damaging failure of the two.

An incomplete sense-amp contact and an incomplete I/O-driver contact fail very differently, which is why the etch margin gets biased toward protecting the small ones. A marginal contact on a large I/O driver transistor typically still conducts, just with somewhat elevated resistance that a circuit designer sized with margin for in the first place; a marginal contact on a sense-amp transistor can unbalance an already delicate differential pair enough to corrupt the amplifier's read decision entirely, which is a functional failure rather than a performance degradation — this asymmetry in failure severity, not just RIE lag's physics, is the real reason the etch recipe gets tuned around the smallest, most sensitive contacts on the periphery rather than split evenly across the full size range.

This step is where the periphery's silicide strategy and contact strategy have to agree with each other, not be designed independently. A self-aligned silicide layer on the source/drain regions lowers the resistance the contact etch has to punch through to reach silicon, but the silicide's own thickness and the contact etch's selectivity against it are co-designed parameters — an etch recipe qualified without accounting for the actual silicide stack underneath can either punch through the silicide into the junction (an electrical leakage risk) or stop short of it (a resistance risk), which is why periphery contact etch qualification always happens against the final silicide stack rather than against bare silicon.

Read through a one-recipe-two-targets lens, the peripheral source/drain contact etch is the step where the array's manufacturing philosophy — make every feature identical so one recipe serves millions of instances — breaks down completely, replaced by a single etch that has to satisfy a sense amplifier's microscopic contact and an I/O driver's oversized one at the same time, with the smaller one setting the real process requirement.