29,258 technical terms and definitions
refresh controller DRAM, tREFI DRAM, tRFC refresh cycle time, per-bank refresh, REFpb, all-bank refresh, refresh overhead DRAM, DRAM temperature compensated refresh
DRAM Refresh Controller: Row-Scheduling Architecture, the Refresh-Tax Theory, and Per-Bank Refresh Application The refresh controller is the part of DRAM that never gets to rest.…
dram refresh cycle optimization prediction, dram refresh cycle, refresh cycle optimization, cycle optimization prediction, dram refresh, refresh cycle, cycle optimization
DRAM Refresh Cycle Optimization Prediction with Machine Learning Introduction & Motivation DRAM Refresh Cycle Optimization Prediction with Machine Learning addresses a central…
dram, dynamic random-access memory, 1T1C DRAM, DRAM cell architecture, DRAM refresh, DRAM storage capacitor, DRAM memory matrix, DRAM sensing, dram refresh fail bit count, fail bit count prediction
DRAM: Dynamic Random-Access Memory — Architecture, Retention Physics, and 1T1C Scaling Dynamic Random-Access Memory (DRAM) is the fundamental working memory of computing: it…
dram refresh interval drift prediction, dram refresh interval, refresh interval drift, interval drift prediction, dram refresh, refresh interval, interval drift, drift prediction
DRAM Refresh Interval Drift Prediction with Machine Learning Introduction & Motivation DRAM Refresh Interval Drift Prediction with Machine Learning addresses a central problem…
dram refresh overhead and capacity trade-offs, dram refresh overhead, refresh overhead capacity, overhead capacity trade-offs, dram refresh, refresh overhead, overhead capacity
DRAM Refresh Overhead and Capacity Trade-Offs Introduction & Motivation DRAM Refresh Overhead and Capacity Trade-Offs addresses a central problem in memory process control…
dram refresh rate optimization, dram refresh rate, refresh rate optimization, dram refresh, refresh rate, rate optimization
DRAM Refresh Rate Optimization with Machine Learning Introduction & Motivation DRAM Refresh Rate Optimization with Machine Learning addresses a central problem in DRAM refresh…
dram memory optimizing refresh rates in dram to balance power and data retention, dram memory optimizing, memory optimizing refresh, optimizing refresh rates, refresh rates dram, dram memory
DRAM Memory: Optimizing refresh rates in DRAM to balance power and data retention Introduction & Motivation DRAM Memory: Optimizing refresh rates in DRAM to balance power and data…
optimizing refresh rates in dram to balance power and data retention, optimizing refresh rates, refresh rates dram, rates dram to, dram to balance, to balance power, balance power data
Optimizing refresh rates in DRAM to balance power and data retention Introduction & Motivation Optimizing refresh rates in DRAM to balance power and data retention addresses…
dram refresh row hammer prediction, dram refresh row, refresh row hammer, row hammer prediction, dram refresh, refresh row, row hammer, hammer prediction
DRAM Refresh Row Hammer Prediction with Machine Learning Introduction & Motivation DRAM Refresh Row Hammer Prediction with Machine Learning addresses a central problem in DRAM…
CD shrink, photoresist trim etch, isotropic trim DRAM, critical dimension correction, lithography resolution limit
A resist trim, also called CD shrink, is a deliberate isotropic etch that shrinks a photoresist pattern's critical dimension after lithography has already finished, used…
photoresist rework, litho rework strip, cd-sem overlay inspection, wafer scrap recovery
Every single round covered in this entire project, from the storage-node hole etch through the bump and RDL opening, has moved a wafer forward — removing material to build toward…
next-generation dram technology, next-generation dram, dram technology
Next-Generation DRAM Technology Introduction & Motivation Next-Generation DRAM Technology addresses a central problem in memory process control and capacity-per-die prediction…
row hammer DRAM, rowhammer, aggressor row victim row, target row refresh, TRR DRAM, activation threshold DRAM, PRAC DDR5, refresh management RFM
DRAM Row Hammer: Disturbance Architecture, the Activation-Threshold Theory, and Target Row Refresh Application Row hammer is what happens when the same electrical margins this…
high bandwidth memory HBM, DRAM cell capacitor, DDR5 LPDDR5 memory, memory wall bandwidth
DRAM scaling technology for HBM applications has pursued capacity and bandwidth gains through 3D die stacking and wider interfaces, as a complement to, rather than a full…
sense amplifier DRAM, cross-coupled latch DRAM, folded bitline DRAM, bit line isolation transistor, DRAM bit line equalization, sense amp offset DRAM, Pelgrom law DRAM, regenerative sense amplifier
DRAM Sense Amplifier: Cross-Coupled Latch Architecture, Regenerative Feedback Theory, and the Folded-Bitline Application The sense amplifier is where a DRAM read actually becomes…
si sige alternating stack, sacrificial sige epitaxy, 3d dram sige channel, gaa nanosheet sacrificial layer
The SiGe superlattice stack etch cuts a single continuous opening through an epitaxially grown stack of alternating silicon and silicon-germanium layers, and it produces…
salicide block, precision resistor silicide, esd structure silicide block, fuse element silicide
The silicide block etch inverts the logic every other etch in this project has followed: instead of opening a pattern across a handful of special locations, it opens the pattern…
SPT spacer etch, SADP spacer, SAQP spacer, anisotropic sidewall spacer, self aligned multi patterning
The spacer etch is the single step in self-aligned patterning where a conformal oxide or nitride film, deposited evenly over every mandrel, gets etched back until only vertical…
field recess, step height DRAM, saddle fin exposure, wet vs dry recess, reference datum etch
The STI oxide recess etches the trench fill down below the silicon surface by a specific, carefully targeted depth after the trench has already been cut and filled, and that one…
DRAM shallow trench isolation, shallow trench isolation DRAM, DRAM cell isolation, STI corner leakage, buried word line isolation, saddle fin transistor, DRAM active area isolation, STI gap fill DRAM, cell-to-cell leakage DRAM, STI aspect ratio scaling
DRAM STI: Shallow Trench Isolation Architecture, Corner-Leakage Theory, and the Cell-to-Cell Isolation Moat Shallow trench isolation (STI) is the etched, oxide-filled moat that…
dram storage capacitor aspect ratio prediction machine learning, dram storage, capacitor aspect ratio, dram sem, dram storage capacitor aspect ratio prediction
DRAM Storage Capacitor Aspect Ratio Prediction with Machine Learning Introduction & Motivation DRAM Storage Capacitor Aspect Ratio Prediction with Machine Learning addresses…
SNC, buried contact BC etch, self aligned contact DRAM, nitride fence etch, landing pad contact
The storage node contact — SNC, or BC (Buried Contact) depending on the maker — is the bitline contact's sibling on the opposite side of the DRAM cell, etched self-aligned between…
cylinder etch, mold etch DRAM, capacitor etch DRAM, high aspect ratio etch, bowing twisting not open defects, mold dip out
The storage node hole etch — also called the cylinder etch or mold etch — is widely considered the single hardest etch step in all of DRAM manufacturing, because it has to punch…
well strap contact, body strap contact, latch up prevention dram, substrate tie down contact
The strap contact etch lands a via directly on the well or substrate material itself rather than on any transistor's source or drain, and it exists almost entirely as insurance…
top support open, mid support open, mesh lattice open, capacitor cylinder bracing, mold dip out preparation
The support open etch punches a mesh or lattice of windows through the mold stack's nitride support layers, a pattern that looks almost like damage compared to every other etch…
dram technology roadmap, dram technology, technology roadmap
DRAM Technology Roadmap Introduction & Motivation DRAM Technology Roadmap addresses a central problem in memory process control and capacity prediction: how to Predict capacity…
dram cell capacitor, dram high k capacitor, 4f2 dram cell, dram refresh reliability
DRAM technology scaling faces increasing physical challenges as cell capacitor size and access transistor dimensions continue shrinking, since a DRAM cell's stored charge…
scribe line pcm, process control monitor etch, dicing kerf test structures, wafer electrical probing
The test-key and scribe-line open etch finishes off structures that are built with the exact same process fidelity as the real array and periphery, deliberately placed where every…
plate etch dram capacitor, TiN top electrode, SiGe top electrode, capacitor plate contact etch
The top electrode etch is the step that caps off a DRAM cell capacitor by patterning the TiN or SiGe plate layer draped over every storage node cylinder in the array, cutting it…
US-Japan memory conflict, dumping, commodity memory competition, US firms exit DRAM, semiconductor trade dispute
The DRAM trade war refers to the broad economic and political conflict, peaking in the 1980s, over dynamic memory chips between the United States and Japan, as Japanese…
hbm backside passivation, tsv tip exposure passivation, backside rdl foundation, backside conformal coating dram
The backside passivation open looks, on paper, like a repeat of the front-side passivation open covered earlier in this project, but it serves the opposite functional role…
hbm backside reveal, tsv tip protrusion, wafer thinning tsv, 3d stack bonding dram
The TSV backside reveal etch has to stop exactly at a target that isn't sitting at a known, fixed depth the way almost every prior endpoint in this project has — the buried tip…
through silicon via etch, bosch process dram, hbm tsv, via last via middle via first
The TSV etch is the first step in this entire project that cuts through single-crystal bulk silicon substrate itself rather than any deposited film, and that single difference…
tsv bottom liner punch, tsv isolation liner, tsv leakage reliability, tsv via floor contact
The TSV liner open etch has to treat the exact same insulating film completely differently depending on where it sits inside a single via, clearing it from the via's floor while…
twin cell DRAM, differential sense amplifier DRAM, dummy cell reference DRAM, common-mode rejection DRAM, radiation hardened DRAM, twin cell sensing
DRAM Twin-Cell Reference: Differential Sensing Architecture, Common-Mode Cancellation Theory, and the Reliability-Density Trade-Off A twin-cell reference replaces the sense…
vct pillar etch, vertical channel transistor dram, pillar diameter uniformity, emerging dram cell architecture
Every etch covered across this entire project so far, from the storage-node hole through the TSV and even the bevel etch, has removed material to create a cavity or a cleared…
interlayer via etch, dual damascene via, via resistance scaling, electromigration via reliability
The via etch cuts the vertical connection between one metal layer and the next, and unlike the M1 trench etch's horizontal mold, it forces a genuine integration decision every…
dram voltage and timing drift prediction, dram voltage timing, voltage timing drift, timing drift prediction, dram voltage, voltage timing, timing drift, drift prediction
DRAM Voltage and Timing Drift Prediction with Machine Learning Introduction & Motivation DRAM Voltage and Timing Drift Prediction with Machine Learning addresses a central problem…
WL cap recess, SiN cap planarization, buried wordline seal, bitline contact surface prep
The WL cap etch-back planarizes a nitride capping layer deposited over the finished buried wordline fill, removing it down to a controlled depth that seals the metal or poly gate…
dual work function wordline, GIDL suppression, buried wordline gate fill, DRAM channel control
The WL poly recess etches back a polysilicon fill inside the buried wordline trench to a specific depth, a step that only exists at all because some DRAM designs give the top…
dram word line resistance variation prediction, dram word line, word line resistance, line resistance variation, resistance variation prediction, dram word, word line
DRAM Word Line Resistance Variation Prediction with Machine Learning Introduction & Motivation DRAM Word Line Resistance Variation Prediction with Machine Learning addresses…
mostek mk4096 reference, pin count density chart, 4k dram reference diagram
RAS/CAS Multiplexing — the Waveform That Saved Half the Pins Mostek's MK4096, and the addressing trick every later DRAM generation inherited 1K DRAM worked, but systems wanted…
4k dram, dram4k 1973
Confront the 1K DRAM Density Wall The 1968 Dennard one-transistor, one-capacitor cell solved the structural problem of dense dynamic memory, and the parts that followed it through…
mostek mk4096, dram4k 1973
Define the 4K-Bit Density Target The generation that followed 1K DRAM set its target at 4,096 bits per chip, a four-fold jump in a single generation rather than an incremental…
ti tms4030, dram4k 1973
Name the Address-Pin-Explosion Problem Doubling the number of address bits needed to reach 4K density meant, under the old addressing convention, doubling the number of address…
ras cas multiplexing, dram4k 1973
Introduce Multiplexed Addressing as the Fix The fix that defined this generation was to stop giving every address bit its own permanent pin and instead share the same physical…
dram pin count, dram4k 1973
Explain Row-Address-Strobe Timing With address pins now shared across two phases, the chip needed a signal telling it exactly when the row half of the address was valid on those…
dram cost per bit, dram4k 1973
Explain Column-Address-Strobe Timing After the row address was latched and the row of cells was active, the chip needed a second signal to say when the column half of the address…
4k dram, dram4k 1973
Compare Pin Counts Before and After Multiplexing Without multiplexed addressing, a 4K-bit DRAM needing roughly twelve address bits would have required twelve dedicated address…
mostek mk4096, dram4k 1973
Introduce the Mostek MK4096 as the Generation-Defining Part Mostek shipped the MK4096 as the part that defined this generation commercially, pairing the 4,096-bit array…