3,801 technical terms and definitions
photolithography step 9 resolution limits diffraction, resolution limits and diffraction
Resolution Limits and Diffraction: Step 9 The physics barrier to pattern fineness and techniques to overcome it Step 9 explores the diffraction limit — why we cannot print…
photolithography step 17 self-aligned double patterning, self aligned double patterning
Self-Aligned Double Patterning: Step 17 Mandrel creation, spacer deposition, line doubling without trim alignment This step advances photolithography by addressing [topic]. Step…
photolithography stepper alignment overlay prediction, photolithography stepper alignment, stepper alignment overlay, alignment overlay prediction, stepper alignment
Photolithography Stepper Alignment Overlay Prediction with Machine Learning Introduction & Motivation Photolithography Stepper Alignment Overlay Prediction with Machine Learning…
photoluminescence spectroscopy, pl spectroscopy, semiconductor photoluminescence, band edge emission
Photoluminescence spectroscopy asks what happens after a semiconductor absorbs light energetic enough to create excited carriers. Some electrons and holes recombine radiatively…
pl mapping, wafer photoluminescence mapping, semiconductor pl imaging, photoluminescence uniformity map
Photoluminescence spectroscopy asks what happens after a semiconductor absorbs light energetic enough to create excited carriers. Some electrons and holes recombine radiatively…
reticle, mask blank, mask fabrication, e-beam mask writing, phase shift mask
Photomask (reticle): the master pattern for a chip layer. A photomask controls where exposure light reaches the wafer. Projection optics form a smaller image in photoresist…
photomask fabrication, phase-shift mask, psm, reticle manufacturing, mask blank defect, ebeam mask writing
Photomask fabrication, phase-shift mask engineering, and nanoscopic defect repair constitute the foundational master-patterning technologies that enable optical projection…
mask blank defect, mask pattern writing, phase shift mask, mask repair
Photomask fabrication, phase-shift mask engineering, and nanoscopic defect repair constitute the foundational master-patterning technologies that enable optical projection…
EUV mask, mask blank, absorber, reticle fabrication
Photomask fabrication, phase-shift mask engineering, and nanoscopic defect repair constitute the foundational master-patterning technologies that enable optical projection…
lithography
Photon shot noise is the fundamental statistical variation in the number of photons arriving at any given point on the wafer during lithographic exposure. Since photons are…
lithography
A photon sieve is an alternative optical element for EUV lithography that uses a pattern of precisely placed pinholes in an opaque membrane to focus light through diffraction…
photonic integrated circuit, silicon photonics design, ring resonator optical, mach zehnder modulator
Silicon photonics and optical I/O technologies integrate high-density optical waveguides, electro-optic modulators, photodetectors, and heterogeneous laser sources onto standard…
mach zehnder modulator mlp, optical matrix vector multiply, silicon photonic chip ai, optical memory bottleneck
Photonic Computing: Optical Matrix-Vector Multiplication via Mach-Zehnder Interferometer Mesh — exploits wavelength-division multiplexing and optical parallelism to achieve…
PIC, fabrication, waveguide
Photonic Integrated Circuit PIC Fabrication is an advanced manufacturing process technology that integrates multiple optical components (waveguides, modulators, switches…
silicon photonics fabrication, optical waveguide technology, photonic chip manufacturing, integrated optical components
Silicon photonics and optical I/O technologies integrate high-density optical waveguides, electro-optic modulators, photodetectors, and heterogeneous laser sources onto standard…
silicon photonics manufacturing, pic foundry, optical waveguide semiconductor, photonic chip process
Silicon photonics and optical I/O technologies integrate high-density optical waveguides, electro-optic modulators, photodetectors, and heterogeneous laser sources onto standard…
silicon photonics, optical transceiver, co packaged optics cpo, photonic semiconductor
Silicon photonics and optical I/O technologies integrate high-density optical waveguides, electro-optic modulators, photodetectors, and heterogeneous laser sources onto standard…
silicon photonics manufacturing, optical transceiver chip, photonic waveguide fabrication, pic semiconductor process
Silicon photonics and optical I/O technologies integrate high-density optical waveguides, electro-optic modulators, photodetectors, and heterogeneous laser sources onto standard…
lithography, chemically amplified resist, photoresist chemistry, euv resist
Photoresist (PR / Resist) Photoresist is a light-sensitive patterning material that can serve as a temporary etch mask. Connect the name to its role Document whether this film is…
chemically amplified resist, euv photoresist, resist resolution limit, metal oxide resist
Photoresist chemistry and track coat-bake-develop processing constitute the photochemical foundation of semiconductor patterning, converting aerial optical and extreme ultraviolet…
positive negative photoresist, chemically amplified resist, euv photoresist development, photoresist processing lithography
Photoresist chemistry and track coat-bake-develop processing constitute the photochemical foundation of semiconductor patterning, converting aerial optical and extreme ultraviolet…
chemically amplified resist, euv photoresist, resist development process, dry resist metal oxide
Photoresist chemistry and track coat-bake-develop processing constitute the photochemical foundation of semiconductor patterning, converting aerial optical and extreme ultraviolet…
euv photoresist, chemically amplified resist, metal oxide resist mor, resist sensitivity resolution
Photoresist chemistry and track coat-bake-develop processing constitute the photochemical foundation of semiconductor patterning, converting aerial optical and extreme ultraviolet…
positive tone resist mask polarity, negative tone development euv lithography, photoacid generator crosslinking resist chemistry
Photoresist is named "positive" or "negative" by direct analogy to photographic film, and the analogy is exact enough to use as the entire definition — in a positive-tone resist…
Photovoltaics: Semiconductor Junctions, Solar Cell Physics, and System Design Photovoltaic (PV) energy conversion transforms solar radiation directly into electricity via…
autonomous pd, machine learning pd, ml placement, ai eda, ml chip design
Machine Learning in Physical Design (AI-EDA) is the application of neural networks, reinforcement learning, and other ML techniques to accelerate and improve placement, routing…
block placement chip, macro placement, floorplan optimization, die area utilization
Chip Floorplanning is the critical early-stage physical design activity that determines the spatial arrangement of major functional blocks (hard macros, soft macros, memory…
chip floorplan methodology, block placement floorplan, floorplan power planning, hierarchical floorplanning
Physical Design Floorplanning is the critical early-stage physical implementation step that defines the chip's spatial organization by determining die size, placing hard macro…
block level pnr, top level integration, chip assembly
Hierarchical Physical Design is the divide-and-conquer methodology for implementing large SoCs where the chip is partitioned into independently designed blocks (macros/partitions)…
ring oscillator puf, sram puf bit, hardware fingerprint chip, puf authentication security
Physical Unclonable Function (PUF) Every chip that comes off the same mask set is, in principle, identical — but transistor-level manufacturing variation means no two dies are…
physical vapor, deposition process modeling, ml pvd, physical vapor deposition, vapor deposition process, vapor deposition, deposition process, process modeling
Physical Vapor Deposition Process Modeling Introduction & Motivation Predicting PVD process outcomes through ML accelerates film deposition development for coatings, electronics…
physical vapor deposition sputtering rate prediction, physical vapor deposition, vapor deposition sputtering, deposition sputtering rate, sputtering rate prediction
Physical Vapor Deposition Sputtering Rate Prediction with Machine Learning Introduction & Motivation Physical Vapor Deposition Sputtering Rate Prediction with Machine Learning…
physics modeling, differential equations, semiconductor physics, device physics, transport equations, heat transfer equations, process modeling, pde semiconductor
Physics-based semiconductor modeling converts conservation laws, material relations, geometry, and operating conditions into a boundary-value or initial-boundary-value problem…
pick-and-place accuracy, packaging
Test and packaging turn a completed wafer into a dependable product. Fabrication creates transistors and interconnect, but it does not prove that every die works, connect the die…
piezoelectric mems actuator fabrication yield prediction machine learning, piezoelectric mems, actuator fabrication yield, mems, piezoelectric mems actuator
Piezoelectric MEMS Actuator Fabrication Yield Prediction with Machine Learning Introduction & Motivation Piezoelectric MEMS Actuator Fabrication Yield Prediction with Machine…
piezoresponse force microscopy, pfm, metrology
Piezoresponse Force Microscopy (PFM) is a contact-mode scanning probe technique that maps the local piezoelectric response of a material by applying an AC voltage through…
pin diode rf switch, pin diode photodetector, pin forward bias minority carrier, pin variable resistor
PIN Diode is the p-i-n junction with intrinsic (i) layer enabling efficient photodetection and RF switching through minority carrier storage and variable resistance under forward…
pga, packaging
Pin grid array is the package architecture with pins arranged in a two-dimensional grid on the package underside for high pin-count connectivity - it supports dense interconnect…
rca clean, wafer cleaning, surface preparation, sc-1, sc-2, piranha clean, marangoni drying, clean tech
RCA cleaning and advanced semiconductor surface preparation constitute the sequential wet chemical and physical processes engineered to remove organic residues, sub-micron…
lithography pitch, contacted poly pitch, cpp, minimum metal pitch, mmp, feature pitch, pattern pitch, semiconductor pitch, node scaling, lithography
Lithography pitch is the fundamental center-to-center distance between repeating identical features on a semiconductor wafer, defining the ultimate packing density, interconnect…
advanced packaging
Pitch Scaling in Advanced Packaging is the progressive reduction of interconnect pitch (center-to-center distance between adjacent connections) between stacked dies or between die…
hoerni 1959 lateral diffusion insight surface junction, planar transistor 1959 junction under oxide recognition, silicon planar 1959 realization not new fabrication technique
Recognize That the Masking Oxide Already Covered the Junction the Whole Time: The Insight, Not the Material 1. Why the Lateral Diffusion Everyone Already Knew About Was the Whole…
hoerni 1959 contact window margin lateral diffusion design, planar transistor 1959 window inside diffused region oxide intact, silicon planar 1959 reuses photolithography new purpose
Open Small Contact Windows Through the Oxide by Photolithography: A New Reason for an Old Window 1. Why This Window Serves a Completely Different Purpose Than Every Earlier One…
hoerni 1959 metal etch undercut gap base emitter short, planar transistor 1959 second mask aluminum interconnect lines, silicon planar 1959 metal patterned not semiconductor
Pattern the Metal Into Interconnect Lines by a Second Photolithographic Mask: The Same Undercut, a New Way to Fail 1. Why the Gap Between Two Contacts Now Carries the Risk…
contact mask aligner equipment for 1959 photolithography, alignment tolerance between contact window and metal mask
Align the Second Mask to the First by Hand Under a Microscope: The Equipment Behind Step 3 and Step 6's Two Photographic Steps 1. Why Two Photolithographic Masks Only Work…
jean hoerni planar process patent application 1959, fairchild semiconductor planar process patent claim scope
File the Patent on the Step This Series Refused to Take: Hoerni's Claim, Not Just His Idea 1. Why the Insight at Step 1 and Step 2 Needed a Name and a Filing Date, Not Just…
planar process transistor, oxide masking photolithography diffusion, hoerni planar process, junction termination under oxide
The Planar Process: Oxide Masking, Lateral Patterning & Why the Junction Finally Went Under Glass Every process this lineage has covered so far — point-contact whiskers, alloy…
plasma process, semiconductor plasma, plasma processes
A semiconductor plasma is a weakly ionized gas where fewer than 1 in 300 particles carry charge — yet those few charged particles control 40–50% of all processing steps in…
advanced packaging
Plasma-Activated Bonding (PAB) is a surface treatment technique that uses plasma exposure to dramatically enhance direct wafer bonding strength — breaking surface bonds…
plasma chamber seasoning and first wafer effect mitigation with machine learning, plasma chamber seasoning first wafer effect mitigation machine learning, se
Plasma Chamber Seasoning and First-Wafer Effect Mitigation with Machine Learning Introduction & Motivation Plasma Chamber Seasoning and First-Wafer Effect Mitigation with Machine…