453 technical terms and definitions
Particle Source Attribution for Semiconductor Yield Management Particle Source Attribution for Semiconductor Yield Management Introduction Particle Source Attribution…
Physics-Informed Machine Learning for Semiconductor Yield Management Physics-Informed Machine Learning for Semiconductor Yield Management Introduction Physics-Informed Machine…
Predictive Maintenance for Semiconductor Yield Management Predictive Maintenance for Semiconductor Yield Management Introduction Predictive Maintenance for Semiconductor Yield…
Process Window Optimization for Semiconductor Yield Management Process Window Optimization for Semiconductor Yield Management Introduction Process Window Optimization…
Production Qualification for Semiconductor Yield Management Production Qualification for Semiconductor Yield Management Introduction Production Qualification for Semiconductor…
Real-Time Data Quality for Semiconductor Yield Management Real-Time Data Quality for Semiconductor Yield Management Introduction Real-Time Data Quality for Semiconductor Yield…
Recipe Transfer for Semiconductor Yield Management Recipe Transfer for Semiconductor Yield Management Introduction Recipe Transfer for Semiconductor Yield Management is…
Reliability Lifetime Prediction for Semiconductor Yield Management Reliability Lifetime Prediction for Semiconductor Yield Management Introduction Reliability Lifetime Prediction…
Root Cause Analysis for Semiconductor Yield Management Root Cause Analysis for Semiconductor Yield Management Introduction Root Cause Analysis for Semiconductor Yield Management…
Run-to-Run Control for Semiconductor Yield Management Run-to-Run Control for Semiconductor Yield Management Introduction Run-to-Run Control for Semiconductor Yield Management is…
Sensitivity Analysis for Semiconductor Yield Management Sensitivity Analysis for Semiconductor Yield Management Introduction Sensitivity Analysis for Semiconductor Yield…
Sensor Drift Compensation for Semiconductor Yield Management Sensor Drift Compensation for Semiconductor Yield Management Introduction Sensor Drift Compensation for Semiconductor…
Spatial Uniformity Control for Semiconductor Yield Management Spatial Uniformity Control for Semiconductor Yield Management Introduction Spatial Uniformity Control…
Surface Roughness Reduction for Semiconductor Yield Management Surface Roughness Reduction for Semiconductor Yield Management Introduction Surface Roughness Reduction…
Thermal Management for Semiconductor Yield Management Thermal Management for Semiconductor Yield Management Introduction Thermal Management for Semiconductor Yield Management is…
Tool Drift Detection for Semiconductor Yield Management Tool Drift Detection for Semiconductor Yield Management Introduction Tool Drift Detection for Semiconductor Yield…
Traceability and Genealogy for Semiconductor Yield Management Traceability and Genealogy for Semiconductor Yield Management Introduction Traceability and Genealogy…
Transfer Learning for Semiconductor Yield Management Transfer Learning for Semiconductor Yield Management Introduction Transfer Learning for Semiconductor Yield Management is…
Uncertainty Quantification for Semiconductor Yield Management Uncertainty Quantification for Semiconductor Yield Management Introduction Uncertainty Quantification…
Virtual Metrology Modeling for Semiconductor Yield Management Virtual Metrology Modeling for Semiconductor Yield Management Introduction Virtual Metrology Modeling…
metrology
Sensitivity in metrology is the change in instrument response per unit change in the measured quantity — mathematically the slope of the calibration curve ( ), sensitivity…
alignment verification, recipe verification, dummy wafer fill, send ahead wafer, tool readiness check, lithography calibration, batch uniformity, automated setup verification, non product wafer
Setup wafers are non-product wafers run specifically to verify that a tool is correctly aligned, properly configured with the right recipe parameters, and genuinely ready…
sti cmp planarization, trench fill oxide deposition, active area definition, isolation oxide densification
Shallow trench isolation (STI), high-aspect-ratio dielectric gap fill, chemical mechanical polishing (CMP), and channel mechanical stress engineering constitute the primary…
sti process flow, sti fill cvd, sti cmp planarization, isolation trench semiconductor
Shallow trench isolation (STI), high-aspect-ratio dielectric gap fill, chemical mechanical polishing (CMP), and channel mechanical stress engineering constitute the primary…
device isolation cmos, sti process fill, lcos isolation, isolation oxide semiconductor
Shallow trench isolation (STI), high-aspect-ratio dielectric gap fill, chemical mechanical polishing (CMP), and channel mechanical stress engineering constitute the primary…
sheet resistance map, sheet resistance uniformity mapping, wafer sheet resistance map, resistivity mapping four point probe
Four-point probe metrology measures sheet resistance by forcing current through two contacts and sensing voltage with two separate contacts, so the voltage channel carries almost…
voltage frequency pass fail map, speed binning, timing guardband, wafer probe test, semiconductor test engineering
A shmoo plot is a two-dimensional pass/fail map produced during chip testing — typically voltage on one axis and frequency (or timing margin) on the other — that shows exactly…
metrology
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…
semiconductor etch, sic dry etching, sic plasma etching, sf6 o2, sic trench etch, etch mask sic
Read SiC dry etching through a plasma-physics and etch-rate/selectivity lens rather than a wet-chemistry lens. Silicon carbide's lattice is locked together by Si–C covalent bonds…
silicon carbide process, sic mosfet, sic wafer, wide bandgap fabrication
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
sic diode switching, sic inverter efficiency, sic device aging, sic gate driver design
Silicon Carbide Power Module is a wide-bandgap semiconductor technology enabling superior high-temperature, high-frequency power switching through improved blocking voltage…
silicon carbide, wide bandgap, sic power
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
sit, self aligned spacer patterning, spacer lithography, sit patterning, pitch halving
Sidewall Image Transfer (SIT) is the self-aligned patterning technique that uses the sidewall spacers deposited on a lithographically defined mandrel as the actual etch mask…
bipolar base collector emitter, heterojunction bipolar transistor fabrication, bicmos process integration, hbt speed cutoff frequency
A silicon-germanium heterojunction bipolar transistor is a vertical NPN device whose epitaxial base changes band structure and doping. Fabrication must grow a low-defect SiGe:C…
snr, metrology
SNR (Signal-to-Noise Ratio) is the ratio of the analytical signal to the noise level — where is the signal intensity and is the noise amplitude, quantifying the quality…
metrology
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…
material science, silicon wafer, diamond cubic lattice, czochralski growth, native oxide, silicon dioxide, intrinsic silicon, electronic-grade silicon, band gap
Silicon is the element nearly every chip on Earth is built from — not because it's the best semiconductor on paper, but because it combines a workable band gap, an extraordinarily…
through silicon via TSV, micro bump pitch, copper to copper bonding, impedance controlled routing, chiplet signal integrity, 2.5D thermal management, thermal via hot spot, chiplet rework, passive substrate routing
A silicon interposer is a passive silicon substrate carrying embedded electrical interconnects that routes signals and power between multiple chiplets mounted on top of it…
photonics, chip, co-design, integration
Silicon Photonics Chip Co-Design is an integrated design methodology combining photonic optical components with electronic control circuits on a single silicon substrate — Silicon…
sic power, sic mosfet, wide bandgap semiconductor
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
sic power device, sic substrate wafer, electric vehicle sic, sic inverter
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
sic substrate manufacturing, sic crystal growth, sic wafer defect, sic epitaxy
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
SiC boule growth, micropipe defect density, basal plane dislocation, wide bandgap power semiconductor, physical vapor transport growth, grind polish SiC hardness, power device reliability, automotive traction inverter, SiC substrate cost
Silicon carbide wafer manufacturing is the crystal growth and wafering process flow that produces wide-bandgap silicon carbide substrates for power semiconductor devices, and it's…
chip compilation, high-level synthesis ambition, automated layout, design abstraction, EDA history
A silicon compiler is a tool or approach that aims to translate a relatively high-level description of a desired chip function into the physical layout of an integrated circuit…
griffith fracture criterion 111 cleavage microcrack, back to back diode screening curve tracer bvcbo bvebo, stereomicroscope edge chipping quality gate ti 1954
Inspect the Bars: Dual Mechanical Crack Screening and Two-Junction Gate Slicing the ingot core into individual matchsticks in Step 23 yielded dozens of isolated silicon bars, but…
silicon latent heat of fusion 1787 kj kg density anomaly, silicon semiconductor to metallic melt transition rf coupling, floating solid silicon chunks optical pyrometer plateau 1414
Melt the Charge: Supplying 1414°C Latent Heat Through an RF Induction Susceptor Reaching silicon's 1414°C melting point on an optical pyrometer looks like a single milestone, but…
advanced packaging, cowos, 2.5d packaging, tsv interposer
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
organic substrate bga, substrate trace routing, package substrate laminate, high density substrate
Advanced Packaging Interposer Substrate is a engineering infrastructure connecting semiconductor dies to external connections through elaborate multi-layer routing networks…
SiN film, PECVD nitride, LPCVD nitride, nitride applications
Silicon Nitride (SiN/Si3N4) Deposition encompasses the CVD processes — primarily LPCVD and PECVD — used to deposit silicon nitride films that serve as etch stops, hard masks…
fdsoi fully depleted, soi wafer fabrication, body biasing fdsoi, soi vs bulk cmos
Silicon-on-Insulator (SOI) substrate engineering, Fully Depleted SOI (FD-SOI) planar architectures, and dynamic back-gate body biasing constitute the engineered substrate…