3,801 technical terms and definitions
chiplet integration, die to die interface, ucle, heterogeneous integration chip
Multi-Die Chiplet Design is the architectural approach of decomposing a monolithic chip into multiple smaller dies (chiplets) that are co-packaged and interconnected — enabling…
chiplet interconnect architecture, ucle chiplet standard, chiplet disaggregation, heterogeneous chiplet integration
Multi-Die Chiplet Design Methodology is the chip architecture approach that disaggregates a monolithic SoC into multiple smaller silicon dies (chiplets) connected through…
chiplet interconnect standard, ucIe chiplet, die to die interface, heterogeneous chiplet
Multi-Die Chiplet Integration is the advanced packaging architecture that decomposes a monolithic SoC into multiple smaller silicon dies (chiplets) interconnected through…
chiplet interconnect technology, chiplet packaging architecture, chiplet die to die interface, chiplet heterogeneous integration
Advanced packaging is the set of technologies that connect, protect and cool silicon after it leaves the fab. It has moved from a cost-driven back-end afterthought to a primary…
chiplet design methodology, multi die eda, die to die interface, heterogeneous integration design
Multi-Die and Chiplet Design Methodology is the EDA and architectural approach to designing systems composed of multiple smaller silicon dies (chiplets) connected through advanced…
reticle limited design, stitch boundary overlay, oversized die lithography field
Multi-Die Reticle Stitching A lithography scanner's exposure field has a hard maximum size — roughly 26mm by 33mm for standard DUV and EUV scanners — and a reticle can only…
chiplet integration methodology, die-to-die interconnect, heterogeneous integration methodology, multi-die partitioning strategy
Advanced packaging is the set of technologies that connect, protect and cool silicon after it leaves the fab. It has moved from a cost-driven back-end afterthought to a primary…
advanced packaging
Multi-Layer Transfer is the sequential process of transferring and stacking multiple thin crystalline device layers on top of each other — building true monolithic 3D integrated…
multi-modal microscopy, correlative microscopy, microscopy data fusion, semiconductor correlative microscopy, hypermodal microscopy
No single microscope sees a semiconductor defect in all the ways that matter. Secondary electrons reveal surface form, diffraction reveals crystal orientation, EDS or EELS reveals…
sadp, saqp, double patterning, self aligned multiple patterning, pitch multiplication, lithography
Self-aligned multiple patterning is the pitch multiplication technique where sub-lithographic circuit features are defined not by direct optical resolution but through…
lithography
Multi-Patterning Decomposition is a computational lithography process that mathematically assigns features of a single design layer to multiple sequential lithographic exposures…
sadp saqp, self aligned patterning, double patterning design, pitch walking, lithography
Self-aligned multiple patterning is the pitch multiplication technique where sub-lithographic circuit features are defined not by direct optical resolution but through…
sadp, saqp, self-aligned double patterning, self-aligned quadruple patterning, pitch division, spacer patterning, lithography
Self-aligned multiple patterning is the pitch multiplication technique where sub-lithographic circuit features are defined not by direct optical resolution but through…
self-aligned quadruple patterning, sadp saqp process flow, pitch splitting techniques, litho-etch-litho-etch process, sadp, saqp
Self-aligned multiple patterning is the pitch multiplication technique where sub-lithographic circuit features are defined not by direct optical resolution but through…
mpw, shuttle, shared wafer, multi project, mpw program
Yes, Multi-Project Wafer (MPW) is a core service enabling cost-effective prototyping by sharing wafer and mask costs — with MPW programs available for 180nm (5K-10K per project)…
multi-project wafer, mpw, business
Multi-project wafer (MPW) is a cost-sharing service where multiple chip designs from different customers are placed on the same reticle, dramatically reducing prototyping…
MPW, shared reticle field, mask cost sharing, die allocation, standard PDK, advanced node access, startup prototyping, rapid tape out iteration, shared wafer dicing
Multi-project wafer service, universally abbreviated MPW, is a cost-sharing fabrication model where multiple chip designs from different, entirely unrelated customers get tiled…
metal layers, wiring layers, vias, interconnect delay, chip wiring
Multilevel interconnect is the use of multiple stacked layers of metal wiring, separated by insulating layers and joined by vertical connections, to wire together the enormous…
packaging
Multiple reflow survival is the ability of a semiconductor package to withstand repeated solder reflow exposures without structural or electrical degradation - it is important…
multiple-detect test patterns, N-detect fault coverage, multi-detect ATPG, fault detection diversity, structural test pattern generation, semiconductor test
N-Detect ATPG and Multiple-Detection Test Pattern Generation N-Detect ATPG and Multiple-Detection Test Pattern Generation Executive Overview N-detect automatic test pattern…
n-type silicon, donor-doped semiconductor, majority electrons, phosphorus-doped silicon, arsenic doping, antimony doping, NMOS
An n-type semiconductor is a semiconductor, most often silicon, that has been doped with donor atoms such as phosphorus, arsenic or antimony so that mobile electrons greatly…
high-na euv lithography, numerical aperture euv, 0.55 na euv, next generation euv
High-NA EUV is the next EUV scanner generation: it keeps the 13.5 nm wavelength but raises numerical aperture from 0.33 to 0.55, giving chipmakers sharper imaging for 2 nm-class…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, confront planar nand's cell-to-cell interference wall
Confront Planar NAND's Cell-to-Cell Interference Wall 1. 1. Confront Planar NANDs Cell to Cell Interference Wall Every NAND flash cell before the move to three dimensions stored…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, confront the tunnel-oxide atomic-scale limit
Confront the Tunnel-Oxide Atomic-Scale Limit 2. 2. Confront the Tunnel Oxide Atomic Scale Limit A second wall sat beside the first, and it was arguably harder to argue around…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, the industry's decision: stop shrinking, go vertical
The Industry's Decision: Stop Shrinking, Go Vertical 3. 3. The Industrys Decision Stop Shrinking Go Vertical Faced with cell-to-cell interference that grew worse every time…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, what going vertical actually changes about the cell
What Going Vertical Actually Changes About the Cell 4. 4. What Going Vertical Actually Changes About the Cell Turning the memory array on its side is not just a packaging trick…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, charge-trap storage replaces the floating gate
Charge-Trap Storage Replaces the Floating Gate 5. 5. Charge Trap Storage Replaces the Floating Gate The core memory mechanism in 3D NAND is charge-trap storage, not the floating…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, the ono film stack: oxide, nitride, oxide
The ONO Film Stack: Oxide, Nitride, Oxide 6. 6. The ONO Film Stack Oxide Nitride Oxide The charge-trap layer never sits by itself against the channel; it is sandwiched between two…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, the macaroni channel: a cylindrical transistor
The Macaroni Channel: a Cylindrical Transistor 7. 7. The Macaroni Channel a Cylindrical Transistor The silicon channel that carries current through a 3D NAND string is not a flat…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, one vertical string replaces many planar cells
One Vertical String Replaces Many Planar Cells 8. 8. One Vertical String Replaces Many Planar Cells Put the macaroni channel and the layer-by-layer word lines together and…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, word-line and control-gate layering
Word-Line and Control-Gate Layering 9. 9. Word Line and Control Gate Layering Each horizontal layer in a 3D NAND stack is built from an alternating pair of thin films: one film…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, manufacturing sequence: stack deposition
Manufacturing Sequence: Stack Deposition 10. 10. Manufacturing Sequence Stack Deposition Before a single channel hole is etched, a 3D NAND die begins as a flat stack…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, manufacturing sequence: channel-hole etch and charge-trap deposition
Manufacturing Sequence: Channel-Hole Etch and Charge-Trap Deposition 11. 11. Manufacturing Sequence Channel Hole Etch and Charge Trap Deposition Once the full alternating stack is…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, why etching more layers gets progressively harder
Why Etching More Layers Gets Progressively Harder 12. 12. Why Etching More Layers Gets Progressively Harder The channel-hole etch described in the previous step does not stay…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, hole bowing and twisting at extreme depth
Hole Bowing and Twisting at Extreme Depth 13. 13. Hole Bowing and Twisting at Extreme Depth Beyond simply slowing down, a channel-hole etch pushed to very high aspect ratio can go…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, multi-deck string stacking as the solution
Multi-Deck String Stacking as the Solution 14. 14. Multi Deck String Stacking as the Solution Rather than pushing one single etch all the way through an ever-taller stack…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, the deck-to-deck overlay and joint challenge
The Deck-to-Deck Overlay and Joint Challenge 15. 15. The Deck to Deck Overlay and Joint Challenge Splitting the stack into multiple decks solves the aspect-ratio problem…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, deck count as a design choice across generations
Deck Count as a Design Choice Across Generations 16. 16. Deck Count as a Design Choice Across Generations The tradeoff described in the previous step — fewer decks means harder…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, cmos-under-array: moving periphery logic beneath the memory
CMOS-Under-Array: Moving Periphery Logic Beneath the Memory 17. 17. CMOS Under Array Moving Periphery Logic Beneath the Memory Every NAND die needs peripheral CMOS logic beyond…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, wafer-to-wafer bonding: joining logic and array face-to-face
Wafer-to-Wafer Bonding: Joining Logic and Array Face-to-Face 18. 18. Wafer to Wafer Bonding Joining Logic and Array Face to Face The specific mechanical and electrical trick that…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, the die-area and cost benefit, and its interaction with multi-deck stacking
The Die-Area and Cost Benefit, and Its Interaction With Multi-Deck Stacking 19. 19. The Die Area and Cost Benefit and Its Interaction With Multi Deck Stacking The direct payoff…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, close: where 3d nand scaling stands today
Close: Where 3D NAND Scaling Stands Today 20. 20. Close Where 3D NAND Scaling Stands Today By the mid-2020s, commercial 3D NAND had moved well past two hundred stacked layers…
floating gate process, charge trap flash ctl, word line patterning nand, nand cell oxide tunnel
3D NAND flash is the memory architecture that escapes planar scaling limits by stacking hundreds of storage layers vertically — each layer is a word-line (gate) wrapping…
3d nand process, charge trap flash, nand string, nand stacking layers
3D NAND flash is the memory architecture that escapes planar scaling limits by stacking hundreds of storage layers vertically — each layer is a word-line (gate) wrapping…
lithography
Nanoimprint lithography (NIL) is a patterning technique that creates nanoscale features by physically pressing a pre-patterned template (mold) into a resist material on the wafer…
nanoimprint lithography defect density prediction, nanoimprint lithography defect, lithography defect density, defect density prediction, nanoimprint lithography
Nanoimprint Lithography Defect Density Prediction with Machine Learning Introduction & Motivation Nanoimprint Lithography Defect Density Prediction with Machine Learning addresses…
nanoimprint lithography defect prediction, nanoimprint lithography defect, lithography defect prediction, nanoimprint lithography, lithography defect, defect prediction
Nanoimprint Lithography Defect Prediction with Machine Learning Introduction & Motivation Nanoimprint Lithography Defect Prediction with Machine Learning addresses a central…
nanoimprint lithography defect prediction machine learning, nanoimprint lithography, defect prediction machine, uv, nanoimprint lithography defect prediction
Nanoimprint Lithography Defect Prediction with Machine Learning Introduction & Motivation Nanoimprint Lithography Defect Prediction with Machine Learning addresses a central…
template based imprint, uv cure imprint resin, nil resolution 10nm, nil defect contact
Nanoimprint Lithography (NIL) is pattern transfer via direct mechanical imprinting of template features into polymer resist, enabling sub-5 nm resolution without photon wavelength…
FET, Gate-All-Around, fabrication, process, gaa, nanosheet
Gate-All-Around (GAA) nanosheet field-effect transistors, Multi-Bridge Channel FETs (MBCFET), and vertically stacked ribbon architectures constitute the advanced three-dimensional…