193nm-lithography
193 nm lithography, 193 nanometer lithography
193 nm lithography specifies the exposure wavelength used by ArF systems. It does not specify a 193-nanometer transistor or require a process with that node name. The same…
3,790 technical terms and definitions
193 nm lithography, 193 nanometer lithography
193 nm lithography specifies the exposure wavelength used by ArF systems. It does not specify a 193-nanometer transistor or require a process with that node name. The same…
248 nm lithography, 248 nanometer lithography
248 nm lithography names an exposure wavelength rather than a technology node. In semiconductor manufacturing the term ordinarily refers to KrF excimer-laser deep-ultraviolet…
25d packaging, 2.5d, 2.5d packaging, advanced packaging 25d, silicon interposer packaging, cowos
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
materials, semiconductor, MoS2, WSe2, graphene
2D Materials in Semiconductors: MoS2, WSe2, and Graphene is atomically-thin layered materials exhibiting unique electronic properties enabling transistors, optoelectronic devices…
scm profiling, ssrm metrology
Two-Dimensional Dopant Profiling is a metrology technique that maps dopant concentration across both depth and lateral dimensions in semiconductor structures. What Is 2D Dopant…
transition metal dichalcogenide, tmd monolayer transistor, mos2 channel transistor, 2d semiconductor device
2D Semiconductor Materials (MoS₂/TMDs) is the family of transition metal dichalcogenide crystals with monolayer thickness exhibiting direct bandgaps and strong light-matter…
mos2 transistor fabrication, molybdenum disulfide, mos2, tmd fet, tmdc channel devices, 2d material transfer, 2d heterostructure integration
Two-Dimensional (2D) Material Transistors: Physics, Materials & Scaling Two-Dimensional (2D) Material Transistors represent the ultimate channel-scaling frontier for semiconductor…
wafer size, wafer diameter, chips per wafer, wafer-size generation, 1970s wafer standard
The 3-inch wafer refers to a generation of silicon wafers roughly three inches in diameter that was a common standard in semiconductor manufacturing during the 1970s, one rung on…
300 mm transition, 300 millimeter wafer transition
The 300 mm transition changed the wafer manufacturing platform rather than the transistor’s basic operating principle. Moving from 200 mm to 300 mm substrates increases…
3d, metrology
3D AFM is an advanced atomic force microscopy technique that measures the three-dimensional profile of high-aspect-ratio semiconductor structures — going beyond conventional…
3d chip stacking and integration, 3d chip stacking, chip stacking integration, 3d chip, chip stacking, stacking integration
3D Chip Stacking and Integration Introduction & Motivation 3D Chip Stacking and Integration addresses a central problem in chip-architecture process control…
3D Heterogeneous Packaging, Interposers, TSVs, Hybrid Bonding, and Cryogenic Quantum Co-Integration 1. Why packaging now limits quantum scaling A superconducting quantum processor…
advanced packaging
Advanced packaging is the set of technologies that connect, protect and cool silicon after it leaves the fab. It has moved from a cost-driven back-end afterthought to a primary…
bs source contact, backside source line routing, bonded wafer source contact, backside metal source connection
Backside source contact is a third way into the same source-line plate that CSL contact fill and side-wall ONO removal already reach — and it exists only because bonded…
onon film stack, silicon nitride silicon dioxide stack, 3d nand deposition, pecvd nand stack, charge trap film stack, opop floating gate stack
The 3D NAND film stack is the foundation every later etch and fill step in the flow depends on: 200 to 300-plus alternating pairs of silicon dioxide and silicon nitride (ONON)…
nand string architecture, charge trap flash memory, 3d nand layer count, nand vertical channel
3D NAND flash is the memory architecture that escapes planar scaling limits by stacking hundreds of storage layers vertically — each layer is a word-line (gate) wrapping…
tsc etch, backside via etch bonded nand, xtacking through silicon contact, bonded wafer backside routing
Through-silicon contact, or TSC, is an etch that simply does not exist in a CMOS-under-array chip, because it only becomes necessary once a design has already bonded two separate…
3d ic tsv chiplet stack, logic memory stacking, 3d power delivery 3d, 3d thermal management stacked, hbm
High-bandwidth memory (HBM) is DRAM stacked vertically and connected to its host through an interface thousands of bits wide, running beside the processor on an interposer rather…
3d chip stacking and thermal coupling between layers, 3d chip stacking, chip stacking thermal, stacking thermal coupling, thermal coupling between, coupling between layers, 3d chip
3D Chip Stacking and Thermal Coupling Between Layers Introduction & Motivation 3D Chip Stacking and Thermal Coupling Between Layers addresses a central problem in thermal process…
3d, advanced packaging
3D Stacking via Bonding is the process of vertically integrating multiple semiconductor dies or wafers by bonding them face-to-face or face-to-back — creating three-dimensional…
wafer size, wafer diameter, chips per wafer, wafer-size transition, 100mm wafer
The 4-inch wafer refers to a generation of silicon wafers roughly four inches in diameter that became a widespread manufacturing standard around the late 1970s and early 1980s…
4d stem, four-dimensional stem, four dimensional scanning transmission electron microscopy, pixelated stem, nanobeam diffraction 4d-stem, semiconductor strain mapping 4d-stem
Conventional STEM turns the signal arriving at a detector into one number at each probe position. That number may form an excellent bright-field, annular dark-field, or high-angle…
150mm wafer, wafer size, chips per wafer, wafer-size transition, cost per chip
The 6-inch wafer, roughly 150 millimeters in diameter, is a generation of silicon wafers that became a manufacturing standard as the industry continued climbing its long ladder…
64Kb DRAM, US-Japan semiconductor competition, commodity memory, DRAM manufacturing, memory trade
The 64-kilobit DRAM is the density generation storing 65,536 bits per chip, four times the 16-kilobit generation, reaching the market around the start of the 1980s, and it is…
200mm wafer, wafer size, automated fab, chips per wafer, high-volume manufacturing
The 8-inch wafer, roughly 200 millimeters in diameter, is a generation of silicon wafers that became a major manufacturing standard, the step beyond the 6-inch wafer, and it is…
first principles simulation, density functional theory, quantum materials modeling, electronic structure calculation, dft semiconductor
Etch Plasma–Surface Ab Initio Molecular Dynamics (AIMD) Modeling follows atomic trajectories while recomputing electronic-structure forces from first principles at every time…
metrology
Aberration-Corrected TEM is a TEM equipped with hardware correctors (multipole lens systems) that eliminate spherical and chromatic aberrations — pushing the resolution limit…
metrology
Accuracy, as a model evaluation metric, is simply the fraction of predictions a model got right — correct predictions divided by total predictions. It's the most intuitive metric…
interposer, chiplet, integration, routing
Active Interposer Design Integration is a silicon substrate containing embedded logic, routing resources, and power management circuits that actively orchestrates communication…
adaptive metrology sampling plan optimization machine learning, adaptive metrology, sampling plan optimization, adaptive metrology sampling plan optimization
Adaptive Metrology Sampling Plan Optimization with Machine Learning Introduction & Motivation Adaptive Metrology Sampling Plan Optimization with Machine Learning addresses…
advanced packaging
Adhesive Bonding is a wafer-level bonding technique that uses polymer adhesive layers to join two substrates — offering the lowest bonding temperature (< 200°C), highest…
dram capacitor technology, dram cell architecture, high k dram capacitor, dram buried wordline
High-bandwidth memory (HBM) is DRAM stacked vertically and connected to its host through an interface thousands of bits wide, running beside the processor on an interposer rather…
aib, advanced packaging
Advanced Interface Bus (AIB) is an open-source die-to-die interconnect standard originally developed by Intel and released under the DARPA CHIPS program — providing a parallel…
193nm immersion lithography, immersion scanner resolution, pellicle lithography, lithography overlay
193nm Immersion Lithography is the workhorse patterning technology that has defined semiconductor manufacturing from the 45nm node through today's most advanced EUV-assisted nodes…
photomask fabrication process, mask blank defect, pellicle euv mask, reticle enhancement technique
Photomask fabrication, phase-shift mask engineering, and nanoscopic defect repair constitute the foundational master-patterning technologies that enable optical projection…
CD-SEM, scatterometry, OCD, critical dimension measurement
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…
semiconductor mathematics, lithography mathematics, computational physics, numerical methods
Advanced Mathematics in Semiconductor Manufacturing 1. Lithography & Optical Physics This is arguably the most mathematically demanding area of semiconductor manufacturing. 1.1…
3d integration, chiplet, chiplets, cowos, hybrid bonding, microbump, tsv, hbm, hbm3e, hbm4, interposer, rdl, tcb, besi, disco, ucie, 2.5d packaging, heterogeneous integration, book 5
Advanced Packaging & 3D Integration: Beyond Moore's Law When the economic and physical scaling of photolithography hit the reticle-size limit ( ), the semiconductor industry…
chiplet heterogeneous integration, 2.5D interposer packaging, fan-out wafer level packaging, cowos
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
advanced packaging and chiplet economics, advanced packaging chiplet, packaging chiplet economics, advanced packaging, packaging chiplet, chiplet economics
Advanced Packaging and Chiplet Economics Introduction & Motivation Advanced Packaging and Chiplet Economics addresses a central problem in manufacturing process control…
cowos info package platforms, 2.5d 3d hbm stacking, ucie die interconnect standard, hybrid bonding package substrate, cowos
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
chip on wafer on substrate, hbm integration cowos, tsmc cowos s l r, silicon interposer packaging
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
heterogeneous integration methods, chiplets
Advanced packaging is the set of technologies that connect, protect and cool silicon after it leaves the fab. It has moved from a cost-driven back-end afterthought to a primary…
fcbga, flip chip bga, abf substrate, coreless substrate, organic interposer packaging
Advanced Packaging Substrates are the organic multilayer circuit boards that mechanically support and electrically connect packaged ICs to printed circuit boards — serving as…
advanced packaging yield reliability prediction machine learning, advanced packaging, yield reliability prediction, csam, advanced packaging yield, packaging yield
Advanced Packaging Yield and Reliability Prediction with Machine Learning Introduction & Motivation Advanced Packaging Yield and Reliability Prediction with Machine Learning…
apc semiconductor, run to run control, feedback feedforward process, fab automation control
Advanced process control (APC) uses measurements, process models, and qualified adjustments to keep semiconductor manufacturing outputs near their targets. Instead of using…
apc semiconductor, run to run control, feedback feedforward process, fab automation control, r2r control, ewma controller, ewma run to run control, metrology delay, apc framework, run to run control tuning, semi e133
Advanced process control is the layer of a fab that chooses what recipe the next lot will run, using what the last lot measured. It is not statistical process control, which…
source mask optimization, smo lithography, full chip smo, inverse lithography technology, opc
Computational Lithography and Optical Proximity Correction constitute the mathematical and algorithmic backbone of sub-wavelength semiconductor patterning. Operating deep within…
semiconductor packaging advanced, fan out wafer level, chiplet packaging
For most of computing history, more performance meant more transistors on one monolithic die. As that path slows, the industry increasingly gains performance through advanced…
advanced packaging predicting layer-to-layer registration accuracy in multilayer substrates using process parameters, advanced packaging predicting, packaging predicting layer-to-layer
Advanced Packaging: Predicting layer-to-layer registration accuracy in multilayer substrates using process parameters Introduction & Motivation Advanced Packaging: Predicting…