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ML Inference & LLM Serving Architecture

The physics and engineering of high-throughput, low-latency machine learning serving — from prefill compute saturation to token decode memory bandwidth bottlenecks.

ML inference is the serving side: weights are fixed, and the job is turning requests into tokens (or predictions) under latency, throughput, and cost constraints. For LLMs specifically, the shape of the problem is set by two very different phases.

Phase 1: Prompt Ingestion

Prefill Phase

Prefill processes the whole prompt at once. It's a big matmul over many tokens, so it's compute-bound — you're chasing FLOPs utilization on the tensor cores. Time-to-first-token lives here.

Primary KPI: Time-to-First-Token (TTFT)
Hardware Limiter: Tensor Core Peak TFLOP/s
Phase 2: Autoregressive Generation

Decode Phase

Decode generates one token at a time. Each step reads the entire weight set and the whole KV cache to produce a single token, so arithmetic intensity is terrible and you're memory-bandwidth-bound. Inter-token latency lives here. This is why an H100's 3.35 TB/s of HBM matters more than its FLOPs for decode, and why batching is the central trick: more sequences per weight-read amortizes the bandwidth cost until you run out of KV cache memory.

Primary KPI: Inter-Token Latency (ITL)
Hardware Limiter: HBM Memory Bandwidth (TB/s)

⚡ That tension drives most of the engineering:

🔄 Continuous Batching

Swap finished sequences out of the batch mid-flight instead of waiting for the slowest one. Biggest single throughput win in practice.

📑 PagedAttention

KV cache in fixed blocks instead of contiguous reservations, killing fragmentation and letting you run much larger batches. vLLM's original contribution.

🔢 Quantization

FP8 or INT4 weights cut bandwidth proportionally. Weight-only (AWQ, GPTQ) helps decode a lot; activation quantization additionally helps prefill compute. FP8 on Hopper/Blackwell is close to free quality-wise; INT4 needs care.

⚡ Speculative Decoding

A small draft model proposes k tokens, the big model verifies them in one forward pass. Trades spare compute for bandwidth, so it's a direct answer to the decode bottleneck. Medusa and EAGLE are the self-drafting variants.

🔀 Prefill/Decode Disaggregation

Run the two phases on separate hardware pools since they want different things. Increasingly standard at scale.

💾 Prefix Caching

Reuse KV for shared system prompts across requests.

🔀 On the Parallelism Side

Tensor Parallelism (TP)
Splits within a layer and needs fast interconnect (NVLink).
Pipeline Parallelism (PP)
Splits across layers and adds bubbles.
Expert Parallelism (EP)
Its own problem for MoE models where routing imbalance dominates.

🛠️ Serving Stacks Worth Knowing

vLLM
Most flexible, fastest-moving open-source serving engine.
SGLang
Strong on structured output and RadixAttention prefix reuse.
TensorRT-LLM
Fastest on NVIDIA hardware if you tolerate the build step.
llama.cpp
The gold standard for edge, Mac metal, and CPU inference.

Interactive Transformer-Chip Inference Simulator

Simulate roofline memory-vs-compute bottlenecks, decode throughput, KV-cache footprint, and batch serving curves on real silicon architectures.

H100 · Llama-70B H100 · 70B FP8 H200 · 70B H100 · Llama-8B B200 · 70B
Accelerator Specifications
Transformer Model Architecture
Serving Workload
Developer API — Call this exact serving performance model over HTTP:
curl -X POST https://www.amemories.com/edge/infer \
  -H "Content-Type: application/json" \
  -d '{"peak_tflops":990,"hbm_bw_gbs":3350,"hbm_cap_gb":80,"params_b":70,
       "hidden_dim":8192,"layers":80,"n_heads":64,"n_kv_heads":8,
       "seq_len":4096,"batch":1,"weight_bytes":2}'
Returns JSON with outputs (decode throughput, prefill throughput, TTFT, latency, bottleneck classification, arithmetic intensity, utilization, memory footprint), the full batch serving curve, and compute node timings.