Datacenter Chip Cooling Loop Simulator

Model whether an AI accelerator stays cool — and worth cooling, then run it: the simulation executes on the ChipFoundryServices distributed compute pool. As training silicon pushes past 700 W–1 kW per package, the heat path stops being “chip → heatsink → air” and becomes a thermal resistance network: from the junction, through two thermal-interface layers (TIM1, TIM2) and a copper lid, into a liquid cold plate (or a two-phase / immersion microchannel evaporator), and out to the facility coolant. Two things gate the design. The thermal budget: the series conduction resistances, the convective film resistance, and the caloric resistance (the coolant heats up as it carries the heat away) sum to theta_JA; the junction temperature Tj = coolant_inlet + Q·theta_JA has to sit under Tj_max with margin. And the cooling overhead: moving coolant costs pump/fan power — pressure drop grows ~flow^1.75, so buying thermal margin with flow burns parasitic watts. The design ships only if it clears both gates. Reduced-order educational model. See also the package thermal, package warpage, dynamic power, electromigration, HBM bandwidth and power-delivery network simulators and the compute-pool status.

Liquid cold plate Two-phase / immersion Air (modest TDP)

Load & limits

Chip TDP 700 W Die edge 26 mm Coolant / air inlet temp 30 °C Max junction temp (Tj max) 105 °C

Cooling mode & fluid

Cooling mode Coolant (liquid modes) Liquid flow rate 2 LPM Air flow (air mode) 60 CFM

Thermal stack

TIM1 thickness (die→lid) 50 µm TIM1 conductivity 5 W/mK Copper lid thickness 2 mm TIM2 thickness (lid→plate) 100 µm TIM2 conductivity 5 W/mK Cold-plate base thickness 2 mm Cold-plate footprint edge 40 mm Fin / microchannel area gain 12×

Pump/fan & budget

Pump / fan efficiency 50 % Cooling overhead budget 5 % of TDP

Junction temperature vs coolant flow — Tj falls as flow rises (the film and caloric resistances drop with flow). The dashed red line is the Tj max limit: the curve must stay below it. The marker (●) is your operating point — below the line the chip is safe, above it it overheats

Left: Tj vs chip power — junction temperature climbs linearly with TDP; it crosses the dashed red Tj max line at the power ceiling (marker ● = your TDP). Right: the thermal resistance stack — each element as a share of theta_JA; the amber bar is the dominant resistance to attack first

Developer API — same simulation over HTTP (load-balanced across the pool):

curl -X POST https://www.chipfoundryservices.com/edge/cooling \
  -H "Content-Type: application/json" \
  -d '{"tdp_w":700,"die_size_mm":26,"coolant_inlet_c":30,"tj_max_c":105,
       "cooling_mode":"cold_plate","coolant":"water","flow_rate_lpm":2,"air_flow_cfm":60,
       "tim1_thickness_um":50,"tim1_conductivity":5,"lid_thickness_mm":2,
       "tim2_thickness_um":100,"tim2_conductivity":5,"plate_base_mm":2,"plate_size_mm":40,
       "fin_enhancement":12,"pump_eff_pct":50,"overhead_budget_pct":5}'

Returns JSON with outputs (theta_ja_c_w, r_tim1_c_w, r_lid_c_w, r_tim2_c_w, r_plate_c_w, r_conduction_c_w, r_convection_c_w, r_caloric_c_w, dominant_resistance, junction_temp_c, tj_headroom_c, meets_thermal, coolant_rise_c, coolant_outlet_c, flow_display, flow_unit, mass_flow_kg_s, film_coeff_w_m2k, wetted_area_cm2, pressure_drop_kpa, pump_power_w, cooling_overhead_pct, meets_efficiency, meets_budget, verdict), the full profile (48-point tj_vs_flow sweep [flow, junction_temp_c] and 48-point tj_vs_tdp sweep [tdp_w, junction_temp_c]), the serving node, and compute_ms. Endpoint aliases /edge/coldplate, /edge/liquidcooling, /edge/heatsink, /edge/immersion, /edge/twophase, /edge/coolingloop, /edge/datacentercooling.

Datacenter Chip Cooling Loop Simulator

What these results mean