29,259 technical terms and definitions
ratio based resistor matching instead of absolute value design, designing circuits for monolithic ics not discrete parts
Design Circuits for Monolithic Integration, Not for Discrete Parts: What a Circuit Designer Had to Unlearn 1. Why a Habit That Served Discrete Design for a Decade Now Costs…
publishing a fixed catalog price for an integrated circuit, selling a logic function as an ordinary stocked part
Publish a Catalog Price and a Part Number: Selling a Function Instead of Negotiating a Contract 1. Why a Fixed Price List Is a Claim About Yield, Not Just About Business This step…
electrical screening and burn in for packaged integrated circuits, early life failure rate reduction before shipment
Screen and Burn In Every Finished Chip Before It Ships: A Test Flow a Discrete Transistor Never Needed 1. Why Testing Once at the Wafer Is No Longer Enough Once a Package Is…
logic family interface specification for integrated circuits, guaranteed fan out and noise margin across a logic family
Specify Fan In, Fan Out, and Noise Margin as a Logic Family, Not a Component: What the Interface Spec Had to Promise 1. Why One Chip's Datasheet Now Has to Promise Something About…
proof that monolithic integrated circuits were commercially viable, micrologic series closes and opens the broader ic industry
Close This Series on the Terms That Made It Work, Not a Named Successor: The Proof That Monolithic Integration Could Be Sold 1. Why This Extension Ends Without Pointing to One…
metrology
Micrometer is a precision mechanical measuring instrument that uses a calibrated screw mechanism to measure dimensions with 1-10 micrometer resolution — one of the most…
micromirror array tilt drift prediction, micromirror array tilt, array tilt drift, tilt drift prediction, micromirror array, array tilt, tilt drift, drift prediction
Micromirror Array Tilt Drift Prediction with Machine Learning Introduction & Motivation Micromirror Array Tilt Drift Prediction with Machine Learning addresses a central problem…
micrometer features, feature-size scaling, process generation, micron-scale chips, scaling phases
The micron era refers to the period in chip manufacturing when the smallest features on integrated circuits were measured in whole micrometers, roughly spanning the time before…
edge ai
MicroNet Challenge is a benchmark competition that challenges researchers to design the most efficient neural networks for specific tasks under extreme parameter and computation…
testing
Microprobing is a failure analysis technique that uses precision needle probes to physically contact internal circuit nodes of integrated circuits — enabling direct electrical…
CPU on a chip, single-chip processor, Intel 4004, fetch-decode-execute, microcontroller vs microprocessor, x86, Federico Faggin
A microprocessor is a complete central processing unit fabricated on a single integrated circuit, pulling the arithmetic, control, and register logic that earlier computers spread…
intel 1971 hoff faggin mazor shima busicom mcs4, 4004 1971 silicon function fixed versus behavior from program, microprocessor 1971 extends persistence into stored instructions
Why a Calculator Chip Project Became a General-Purpose Processor: The First Series Whose Silicon Does Not Fix What the Chip Does 1. Why Every Earlier Series Encoded Its Function…
intel 4004 four bit bcd calculator datapath, 4004 1971 sixteen pin package multiplexed four bit bus, microprocessor 1971 four bit word balances pins and transistors
Choose a 4-Bit Word to Fit the Pin and Transistor Budget 1. Make the Native Word Match the Calculator's Decimal Digit The Intel 4004 chose a four-bit processing word because four…
intel 4004 a1 a2 a3 m1 m2 x1 x2 x3 bus phases, 4004 1971 four bit bus time shares address instruction data, microprocessor 1971 one physical bus changes role by clock phase
Multiplex Address and Data Onto the Same Pins: Time-Share One Physical Path Instead of Dedicating Separate Ones 1. Give the Four Bus Lines a Different Meaning in Each Clock Phase…
intel 4004 opa opr instruction format decoder, 4004 1971 opcode phase qualified control signals, microprocessor 1971 decoded instruction selects internal operation
Build the Instruction Decoder From Gates Already Established: Turn a Stored Bit Pattern Into Control 1. Separate the Operation Code From the Operand or Register Selection Once…
intel 4004 ripple carry adder accumulator carry link, 4004 daa decimal adjust accumulator add six bcd, microprocessor 1971 binary adder supports calculator decimal arithmetic
Build the Arithmetic Unit: Four-Bit Binary Addition With Decimal Correction 1. Make One Ripple-Carry Adder Serve the Accumulator The Intel 4004 performs arithmetic through…
intel 4001 256 by 8 mask programmed rom instruction storage, 4004 1971 external program rom fetch opr opa, microprocessor 1971 stable rom program differs from refreshing dram
Store the Program in a Separate Read-Only Memory Chip: Keep Instructions Stable Outside the Processor 1. Let the 4004 Select Instructions From a 4001 Program ROM The Intel 4004…
intel 4004 phi1 phi2 non overlapping clocks sync, 4004 a1 a2 a3 m1 m2 x1 x2 x3 instruction cycle, microprocessor 1971 clock phases coordinate shared bus ownership
Confront the Clock: Why Multiplexing Forces a Multi-Phase Timing Scheme 1. Distinguish the Two Electrical Clock Phases From the Eight Bus Periods The MCS-4 timing system has two…
intel 4004 10.8 microsecond instruction cycle, 4004 versus discrete logic cost per function, microprocessor 1971 integration reduces system assembly per function
Measure the Instruction Cycle Against a Discrete-Logic Equivalent: Count System Cost, Not Clock Speed Alone 1. Measure What the 4004 Actually Completes in 10.8 Microseconds At…
intel 4004 programmable versus fixed purpose logic, 4004 instruction overhead hardware reuse product variants, microprocessor 1971 programmability trades latency for reusable behavior
Qualify the Tradeoff: Flexibility Against Raw Speed 1. Identify the Work a Programmable Processor Adds Before the Useful Operation A fixed-purpose circuit can connect its inputs…
intel mcs 4 4004 4001 4002 4003 chip set, 4004 fetch decode execute stored program architecture, microprocessor 1971 stored instructions select reusable hardware behavior
Classify and Release: The Architecture Every Later Chip Will Assume 1. Classify the 4004 as a CPU, Not as the Entire Computer The Intel 4004 integrates the central processing…
busicom calculator contract that funded the 4004, price cut traded for exclusivity made it a catalog part
The Contract That Paid for This Series: Busicom's Calculator Order and the Deal Intel Made Instead 1. A Custom-Chip-Set Order, Priced and Scheduled Like Any Other Busicom…
hoff architecture mazor instruction set faggin silicon, random logic layout methodology for silicon gate pmos
Name the Individual Contributions: Hoff's Architecture, Mazor's Instruction Set, Faggin's Silicon 1. Three Distinct Jobs Behind One Chip, Not One Person's Design This series has…
texas instruments tms 1000 single chip computer comparison, design priority versus shipping priority definitional dispute
Survey the Competing Priority Claim: Texas Instruments' TMS 1000 and What "First" Actually Means 1. A Second Chip, Designed Earlier, Shipped Later Texas Instruments began…
intel 8008 ctc terminal request eight bit word, word width tradeoff repeated with a different customer
The Quick Successor: Why the 8008 Shipped Within a Year and Changed the Target Customer 1. A Second Chip Whose Origin Predates the First One's Release Intel's 8008, announced…
4004 2300 transistors 10 micrometer pmos 740 khz, three constraints converging on one clock rate
Put Numbers on the Chip: Transistor Count, Process Node, and Clock Rate Behind Steps 1 Through 10 1. The Figures Earlier Steps Used Qualitatively, Stated Exactly Steps 1 through…
design cost amortized across many customers not one, yield learning needs repeated production runs
Price the Difference: Why a Reusable Processor Beats a Fixed-Function Chip Set on Cost, Not Just Flexibility 1. Step 9's Tradeoff, Converted Into a Cost Model Step 9 of this…
designing for programs that do not exist yet, coverage versus width general versus calculator specific tradeoffs
Design an Instruction Set for Strangers: Tradeoffs Fixed Logic Never Had to Make 1. A New Kind of Design Problem Steps 4 and 5 Did Not Need to Solve Step 4 of this series…
dram 1968 dramscaling 1974 dram64k 1979 named only, bus multiplexing pressure mirrors memory density pressure
Name the Memory Thread This Series Leaned On Without Retelling It 1. Step 6's Program ROM Assumed a Memory Technology This Series Never Built Step 6 of this series describes…
second sourcing intel 8080 lineage multiple manufacturers, architecture portable across fabrication lines not one company
License the Design Itself: Second-Sourcing as a Business Practice This Series Has Not Yet Named 1. A Different Kind of Reuse Than Step 16's Cost Model Describes Step 16 of this…
mechanism and context neither sufficient alone, several named threads no single forced handoff
Close This Extension: What the 4004's Full Story, Technical and Otherwise, Actually Adds Up To 1. Ten Steps of Mechanism, Ten Steps of Context, One Chip Steps 1 through 10 of this…
Microprocessor Architecture: Pipelining, Caches, and Out-of-Order Execution A microprocessor transforms a stream of machine instructions into computed results by orchestrating…
metrology
Microroughness is the surface height variation at spatial wavelengths below ~1 µm (typically 0.01-10 µm) — characterizing the atomic-scale and near-atomic-scale surface texture…
microservice integration testing, microservice integration, integration testing
Microservice Integration Testing Introduction & Motivation Microservice Integration Testing addresses a central problem in verification process control and test-setup-time-seconds…
microservices architecture, service mesh, grpc, kafka, distributed services
microservices is an application architecture that decomposes capabilities into independently deployed services communicating through explicit network contracts. Microservices can…
microservices architecture design, microservices architecture, architecture design
Microservices Architecture Design Introduction & Motivation Microservices Architecture Design addresses a central problem in cloud process control…
microsoft maia, what is microsoft maia
Microsoft Maia is Microsoft's own family of custom Azure AI accelerators, separate from its Cobalt general-purpose CPU program, and it spans at least two documented generations…
microstrip line loss tangent drift prediction, microstrip line loss, line loss tangent, loss tangent drift, tangent drift prediction, microstrip line, line loss
Microstrip Line Loss Tangent Drift Prediction with Machine Learning Introduction & Motivation Microstrip Line Loss Tangent Drift Prediction with Machine Learning addresses…
metrology
Microwave impedance microscopy (MIM) images a sample's local electrical impedance at the nanoscale by scanning a sharp probe tip across the surface and measuring how…
mw pcd measurement, microwave detected photoconductivity, photoconductive decay carrier lifetime, pcd lifetime measurement
Microwave photoconductivity decay measures how quickly a wafer's excess free-carrier population, injected by a short laser pulse, relaxes back toward equilibrium, but instead…
device physics
Mid-gap work function refers to a metal work function positioned roughly midway between the values needed for optimal NMOS and optimal PMOS threshold voltage, historically used as…
code ai
Middle Man is a code smell where a class delegates the majority of its method calls directly to another class without performing any meaningful logic of its own — functioning as…
mol process, middle of line integration, trench silicide, local interconnect mol
Middle-of-line (MOL) centers on two closely linked structures: the trench silicide that runs along the source/drain regions providing low-resistance local interconnect, and…
middle-of-line contact resistance drift prediction, middle-of-line contact resistance, contact resistance drift, resistance drift prediction, middle-of-line contact
Middle-of-Line Contact Resistance Drift Prediction with Machine Learning Introduction & Motivation Middle-of-Line Contact Resistance Drift Prediction with Machine Learning…
local interconnect semiconductor, contact over active gate, middle of line metallization, mol contacts
The middle-of-line module begins once FEOL gate stack and spacer formation is complete, and ends once the contact vias are filled and polished flat, ready for the first metal…
mol, process integration
Middle-of-line process development is the engineering discipline of choosing and integrating the contact and local-interconnect materials and sequence as transistor dimensions…
middle-of-line via resistance prediction, middle-of-line via resistance, via resistance prediction, middle-of-line via, via resistance, resistance prediction
Middle-of-Line Via Resistance Prediction with Machine Learning Introduction & Motivation Middle-of-Line Via Resistance Prediction with Machine Learning addresses a central problem…
multimodal ai
Midjourney is a high-quality text-to-image generation system known for stylized and artistic visual outputs - It is widely used for creative concept generation workflows. What Is…
upgrade, language
AI Code Migration is the use of large language models to automate the conversion of legacy codebases to modern languages, frameworks, or library versions — transforming what was…
business & standards
MIL-HDBK-217 is a historical military reliability handbook defining empirical part-failure-rate prediction methods - It is a core method in advanced semiconductor reliability…