29,259 technical terms and definitions
stack vs heap explained, pointers and references, memory leak dangling pointer, writing a memory allocator
Every variable this series' programming-fundamentals topic described as a "named box" is, underneath the name, just a numeric address into the DRAM this site already covers at…
sram cache design, memory hierarchy chip, embedded memory compiler, register file design
On-Chip Memory Architecture is the design discipline that organizes the hierarchy of registers, SRAM caches, and embedded memories within a processor or SoC — where memory access…
hbm stacking tsv, wide io memory interface, hbm bandwidth density, hbm thermal management, hbm
HBM's memory architecture departs from conventional DRAM module architecture in two coupled ways: vertical die stacking connected by through-silicon vias to increase capacity…
memory array leakage prediction, memory array leakage, array leakage prediction, memory array, array leakage, leakage prediction
Memory Array Leakage Prediction with Machine Learning Introduction & Motivation Memory Array Leakage Prediction with Machine Learning addresses a central problem in memory array…
Memory-Augmented Autoencoder for Anomaly Detection Introduction & Motivation Memory-Augmented Autoencoder for Anomaly Detection addresses a central problem in anomaly detection…
video understanding
Memory-augmented video models are the architectures that attach explicit read-write memory to video encoders so context from earlier clips can influence current predictions - this…
hardware
Memory bandwidth—the rate of data transfer between processor and memory—is often the primary bottleneck limiting AI inference performance. Modern accelerators achieve hundreds…
memory wall, hbm bandwidth, gddr bandwidth, ddr5 bandwidth, bandwidth bound
Memory bandwidth is the sustained rate at which useful bytes move between a processor and a memory level. It sets the performance ceiling for workloads whose arithmetic units…
memory bandwidth allocation and qos, memory bandwidth allocation, bandwidth allocation qos, memory bandwidth, bandwidth allocation, allocation qos
Memory Bandwidth Allocation and QoS Introduction & Motivation Memory Bandwidth Allocation and QoS addresses a central problem in soc-design process control…
memory bandwidth asymmetry and direction-dependent performance, memory bandwidth asymmetry, bandwidth asymmetry direction-dependent, asymmetry direction-dependent performance
Memory Bandwidth Asymmetry and Direction-Dependent Performance Introduction & Motivation Memory Bandwidth Asymmetry and Direction-Dependent Performance addresses a central problem…
HBM stack, high bandwidth memory packaging, HBM3E packaging, HBM4 packaging, TSV DRAM stack, hbm
HBM (high-bandwidth memory) achieves its bandwidth advantage over conventional DRAM primarily through interface width: thousands of data bits per HBM stack versus a few hundred…
hbm2 memory, advanced packaging, memory stacking
HBM2 increased both per-pin data rate and maximum stack height over the original HBM standard, while also introducing pseudo-channel mode, which splits each HBM channel into two…
hbm3 memory, advanced packaging, memory stacking
HBM3 further increased per-pin data rate, maximum stack height, and total capacity per stack relative to HBM2, driven primarily by the growing memory bandwidth demands of large AI…
hbm memory, gpu memory, vram, inference bottleneck, a100, h100
High memory bandwidth, in modern accelerator and GPU design, is achieved primarily through wide, parallel data interfaces rather than higher per-pin clock speed alone, since total…
hbm memory, memory stacking, 3d memory, dram stacking
Achieving high memory bandwidth for data-intensive workloads like AI training and inference requires minimizing the number of separate memory transactions needed to move a given…
hbm strategy, business strategy, memory market
Sustaining high memory bandwidth across an entire accelerator system requires memory technology choice (HBM versus conventional DRAM), interface design, and workload-level memory…
hbm stacking, hbm process, wide io memory, hbm3
Pushing memory bandwidth higher for large-scale AI accelerator deployments increasingly requires HBM stacks with both more dies per stack and higher per-pin data rates…
bandwidth bound kernel, memory throughput, dram bandwidth, bandwidth efficiency, roofline memory
Memory bandwidth optimization at the system level involves both selecting adequately wide and fast memory technology (HBM for the highest-bandwidth accelerator applications)…
memory bandwidth saturation and contention scaling, memory bandwidth saturation, bandwidth saturation contention, saturation contention scaling, memory bandwidth, bandwidth saturation
Memory Bandwidth Saturation and Contention Scaling Introduction & Motivation Memory Bandwidth Saturation and Contention Scaling addresses a central problem in memory process…
shared memory bandwidth efficiency in heterogeneous systems, shared memory bandwidth, memory bandwidth efficiency, bandwidth efficiency heterogeneous, shared memory
Shared Memory Bandwidth Efficiency in Heterogeneous Systems Introduction & Motivation Shared Memory Bandwidth Efficiency in Heterogeneous Systems addresses a central problem…
memory bandwidth sharing and priority allocation, memory bandwidth sharing, bandwidth sharing priority, sharing priority allocation, memory bandwidth, bandwidth sharing
Memory Bandwidth Sharing and Priority Allocation Introduction & Motivation Memory Bandwidth Sharing and Priority Allocation addresses a central problem in memory process control…
memory bandwidth utilization efficiency prediction, memory bandwidth utilization, bandwidth utilization efficiency, utilization efficiency prediction
Memory Bandwidth Utilization Efficiency Prediction with Machine Learning Introduction & Motivation Memory Bandwidth Utilization Efficiency Prediction with Machine Learning…
memory bandwidth utilization prediction, memory bandwidth utilization, bandwidth utilization prediction, memory bandwidth, bandwidth utilization, utilization prediction
Memory Bandwidth Utilization Prediction with Machine Learning Introduction & Motivation Memory Bandwidth Utilization Prediction with Machine Learning addresses a central problem…
self-supervised learning
Memory Bank is a data structure used in contrastive self-supervised learning to store a large collection of negative sample representations — enabling effective contrastive…
memory fence, memory ordering
Memory Barrier / Fence — a CPU instruction that enforces ordering of memory operations, preventing the hardware from reordering reads and writes in ways that break concurrent…
memory barrier synchronization, memory barrier, barrier synchronization
Memory Barrier Synchronization Introduction & Motivation Memory Barrier Synchronization addresses a central problem in systems process control and barrier-overhead-latency-cost…
advanced test & probe
Memory BIST is specialized built-in self-test for embedded memories using programmable march and stress algorithms - MBIST controllers run memory-specific test sequences to detect…
design & verification
A memory BIST (built-in self-test) controller is dedicated on-chip hardware that tests an embedded memory array independently of external test equipment, generating its own…
mbist, built in self test memory, sram bist, memory test pattern
Memory BIST test algorithms are built around the March family of patterns, so named because they march through memory addresses in a defined up or down sequence, performing…
built in self test, mbist, memory test, sram bist, repair analysis
Memory BIST's repair capability, often called BISR (built-in self-repair), extends self-test by automatically mapping a defective memory location to a spare one once a fault is…
mbist controller algorithm, march test pattern memory, bist repair analysis, sram bist test coverage
Memory BIST faces its hardest architectural challenges on multi-port and multi-bank memories, where the March test algorithms developed for simple single-port SRAM do not directly…
memory bist fault coverage prediction, memory bist fault, bist fault coverage, fault coverage prediction, memory bist, bist fault, fault coverage, coverage prediction
Memory BIST Fault Coverage Prediction with Machine Learning Introduction & Motivation Memory BIST Fault Coverage Prediction with Machine Learning addresses a central problem…
mbist architecture controller, mbist march algorithm, mbist repair analysis, mbist self test memory
Memory BIST architecture for a modern SoC typically involves not one controller but a hierarchy, since a chip can contain hundreds of separate embedded memory instances of varying…
memory bist repair analysis prediction, memory bist repair, bist repair analysis, repair analysis prediction, memory bist, bist repair, repair analysis, analysis prediction
Memory BIST Repair Analysis Prediction with Machine Learning Introduction & Motivation Memory BIST Repair Analysis Prediction with Machine Learning addresses a central problem…
memory-bound, bandwidth bound, arithmetic intensity, roofline bandwidth ceiling
Memory bound describes a workload whose elapsed time is limited primarily by data supply rather than arithmetic capability. It explains why enormous advertised FLOPS can remain…
model optimization
Memory-Bound Operations is operators whose performance is limited mainly by memory bandwidth rather than arithmetic throughput - They often dominate latency in real inference…
continual learning
A memory buffer in continual learning is a fixed-size storage that holds representative examples from previously learned tasks, enabling rehearsal and preventing catastrophic…
memory bus architecture, memory bus, bus architecture
Memory Bus Architecture Introduction & Motivation Memory Bus Architecture addresses a central problem in memory-architecture process control and bus-bandwidth-gb-per-sec…
memory bus signal integrity prediction, memory bus signal, bus signal integrity, signal integrity prediction, memory bus, bus signal, signal integrity, integrity prediction
Memory Bus Signal Integrity Prediction with Machine Learning Introduction & Motivation Memory Bus Signal Integrity Prediction with Machine Learning addresses a central problem…
memory cell retention time prediction, memory cell retention, cell retention time, retention time prediction, memory cell, cell retention, retention time, time prediction
Memory Cell Retention Time Prediction with Machine Learning Introduction & Motivation Memory Cell Retention Time Prediction with Machine Learning addresses a central problem…
memory cell variability modeling, memory cell variability, cell variability modeling, memory cell, cell variability, variability modeling
Memory Cell Variability Modeling with Machine Learning Introduction & Motivation Memory Cell Variability Modeling with Machine Learning addresses a central problem in memory cell…
memory design characterizing and predicting cell-to-cell variability in memory arrays, memory design characterizing, design characterizing predicting, characterizing predicting cell-to-cell
Memory Design: Characterizing and predicting cell-to-cell variability in memory arrays Introduction & Motivation Memory Design: Characterizing and predicting cell-to-cell…
characterizing and predicting cell-to-cell variability in memory arrays, characterizing predicting cell-to-cell, predicting cell-to-cell variability, cell-to-cell variability memory
Characterizing and predicting cell-to-cell variability in memory arrays Introduction & Motivation Characterizing and predicting cell-to-cell variability in memory arrays addresses…
processing in memory, near data processing, computational memory units, data movement reduction
Memory-Centric Computing Architectures — Design paradigms that place memory at the center of computation, minimizing data movement by bringing processing capabilities closer…
access pattern
Memory coalescing is a critical GPU optimization where adjacent threads access adjacent memory locations, enabling the hardware to combine multiple memory requests into single…
optimization
Memory coalescing is the access pattern optimization where neighboring threads read or write contiguous addresses in combined transactions - it is one of the highest-impact…
coalesced access, gpu memory access pattern
Memory Coalescing — organizing GPU global memory access patterns so that threads in a warp access consecutive memory addresses, allowing the hardware to combine individual…
coalesced memory access, structure of arrays soa, memory access patterns gpu, stride memory access
Memory Coalescing Optimization is the critical technique of arranging memory access patterns so that threads within a warp access consecutive memory addresses — enabling the GPU…
memory coherence protocol scalability and directory overhead, memory coherence protocol, coherence protocol scalability, protocol scalability directory, memory coherence
Memory Coherence Protocol Scalability and Directory Overhead Introduction & Motivation Memory Coherence Protocol Scalability and Directory Overhead addresses a central problem…
sram macro, memory macro generation, cacti memory, memory ip generator, sram compiler tool
Memory Compiler is the automated EDA tool that generates custom SRAM, ROM, or register file macros for a specific foundry process, automatically producing the full set of design…