792 technical terms and definitions
hamming code quantum, hamming code, code quantum
Hamming Code Quantum Introduction & Motivation Hamming Code Quantum addresses a central problem in quantum process control and hamming-code-classical-quantum prediction: how…
han, graph neural networks
HAN is a heterogeneous graph-attention network that aggregates information across metapaths with attention - Node-level and semantic-level attention combine relation-specific…
hand gesture recognition ar, hand gesture recognition, gesture recognition ar, hand gesture, gesture recognition, recognition ar
Hand Gesture Recognition AR Introduction & Motivation Hand Gesture Recognition AR addresses a central problem in vision process control and gesture-recognition-sign-language…
hand gesture recognition, hand gesture, gesture recognition
Hand Gesture Recognition Introduction & Motivation Hand Gesture Recognition addresses a central problem in robotics process control and gesture-classification-recognition…
Hand Gesture and Pose Recognition Introduction & Motivation Hand Gesture and Pose Recognition addresses a central problem in vision processing and gesture-classification-accuracy…
Hand-Object Interaction Recognition Introduction & Motivation Hand-Object Interaction Recognition addresses a central problem in multimodal learning…
hand pose gesture recognition, hand pose gesture, pose gesture recognition, hand pose, pose gesture, gesture recognition
Hand Pose Gesture Recognition Introduction & Motivation Hand Pose Gesture Recognition addresses a central problem in vision process control and hand-keypoint-detection-fingers…
SOI wafer stack, buried oxide thermal bottleneck, FD-SOI back gate, RF-SOI high resistivity, CZ bulk silicon, SOI cost structure, mechanical support substrate, body biasing, SOI manufacturing
The handle wafer is the thick, mechanically robust silicon substrate that forms the structural foundation of an SOI (silicon-on-insulator) wafer stack, providing nothing but…
advanced packaging
Handle Wafer is a permanent substrate that provides structural support to a thin device layer in bonded wafer structures — unlike a temporary carrier wafer that is removed after…
design & verification
Handshake Protocol is a request-acknowledge communication scheme ensuring reliable data transfer across asynchronous boundaries - It coordinates sender and receiver timing without…
haptic driver actuator response prediction, haptic driver actuator, driver actuator response, actuator response prediction, haptic driver, driver actuator, actuator response
Haptic Driver Actuator Response Prediction with Machine Learning Introduction & Motivation Haptic Driver Actuator Response Prediction with Machine Learning addresses a central…
haptic feedback rendering, haptic feedback, feedback rendering
Haptic Feedback Rendering Introduction & Motivation Haptic Feedback Rendering addresses a central problem in haptic process control and haptic-latency-milliseconds prediction: how…
aspect ratio contact etch high, high-aspect-ratio contact, deep contact etch, sac etch
High Aspect Ratio Contact (HARC) Etch is the plasma etch process that drills narrow, deep holes through thick dielectric stacks to reach the transistor source/drain and gate…
lithography
Hard bake is the post-development thermal treatment used when a patterned resist must become mechanically tougher, less permeable, or more resistant to a subsequent wet or plasma…
hdd, hard drive, IBM 305 RAMAC, platter, read-write head, Winchester disk, magnetic storage
A hard disk drive is a non-volatile storage device that records data as magnetized regions on rapidly spinning, rigid disks called platters, reading and writing them with tiny…
machine learning
Hard Example Mining is a training strategy that focuses the model's learning on the most difficult (highest-loss) examples — instead of treating all training samples equally, hard…
advanced training
Hard example mining is a training method that prioritizes samples with high loss or low confidence - The optimizer focuses on challenging instances to improve decision boundaries…
design
Hard IP is a pre-designed, pre-laid-out block delivered as a fixed physical layout (GDS/OASIS) for a specific process technology. The customer places it in their chip design…
self-supervised learning
Hard Negative Mining is a training strategy in contrastive and metric learning where the most difficult negative examples are specifically selected — focusing the model's learning…
recommendation systems
Hard Negative Mining is negative sampling that prioritizes confusing non-relevant items close to positives - It increases learning signal strength by focusing on difficult ranking…
rag
Hard Negative Mining is the process of selecting difficult non-relevant examples that are semantically close to queries during training - It is a core method in modern engineering…
hard negative mining difficult sample and focus learning, hard negative mining, negative mining difficult, mining difficult sample, difficult sample focus, hard negative
Hard Negative Mining Difficult Sample and Focus Learning Introduction & Motivation Hard Negative Mining Difficult Sample and Focus Learning addresses a central problem in hard…
multi-task learning
Hard parameter sharing is a multi-task architecture where tasks use exactly the same core parameters - All tasks update one shared backbone, maximizing reuse and minimizing model…
Hard Parameter Sharing Multi-Task Networks Introduction & Motivation Hard Parameter Sharing Multi-Task Networks addresses a central problem in multitask learning across several…
Hard Parameter Sharing Multi-Task Networks (Extended Study) Introduction & Motivation Hard Parameter Sharing Multi-Task Networks (Extended Study) addresses a central problem…
Hard Parameter Sharing Multi-Task Networks (Extended Study) Introduction & Motivation Hard Parameter Sharing Multi-Task Networks (Extended Study) addresses a central problem…
Hard Parameter Sharing Multi-Task Networks (Extended Study) Introduction & Motivation Hard Parameter Sharing Multi-Task Networks (Extended Study) addresses a central problem…
prompting techniques
Hard Prompt is a discrete natural-language prompt composed of explicit text tokens written by humans or search methods - It is a core method in modern LLM execution workflows.…
prompt engineering
Hard prompt search is the process of systematically exploring the space of discrete natural language prompts to find prompt text that maximizes a language model's performance on…
hard real-time deadline guarantee, hard real-time deadline, real-time deadline guarantee, hard real-time, real-time deadline, deadline guarantee
Hard Real-Time Deadline Guarantee Introduction & Motivation Hard Real-Time Deadline Guarantee addresses a central problem in real-time process control…
architecture
Hard Routing is discrete routing approach that sends each token to specific experts without fractional blending - It is a core method in modern semiconductor AI serving…
haxpes, metrology
Hard X-ray photoelectron spectroscopy (HAXPES) uses multi-keV photons to produce photoelectrons with higher kinetic energy than conventional laboratory XPS, thereby extending…
hard yield limit prediction, hard yield limit, yield limit prediction, hard yield, yield limit, limit prediction
Hard Yield Limit Prediction with Machine Learning Introduction & Motivation Hard Yield Limit Prediction with Machine Learning addresses a central problem in hard yield limit…
silicon nitride hardmask, carbon hardmask, ashable hardmask, patterning hardmask, hard mask stack
Hardmask Patterning in Semiconductor Etch is the use of inorganic or dense carbon films as etch-resistant intermediate layers between the photoresist and the target film — since…
beol
Hardmask for BEOL is a thin, mechanically robust film deposited over the low-k dielectric — serving as the etch mask during trench and via patterning, because photoresist alone is…
security, trojan, detection, methods
Hardware Security Trojan Detection is a verification methodology identifying malicious hardware modifications inserted by adversaries during design, fabrication, or distribution…
hardware acceleration gpu/tpu, hardware acceleration, acceleration gpu/tpu
Hardware Acceleration GPU/TPU Introduction & Motivation Hardware Acceleration GPU/TPU addresses a central problem in ml-hardware process control and acceleration-speedup-factor…
hardware acceleration, accelerator hardware, gpu tpu fpga asic accelerator
Hardware accelerator definition and engineering boundary. is a dedicated compute engine that performs a bounded class of operations faster or with less energy than…
model optimization
Hardware-Aware Design is model architecture and kernel design tuned to specific accelerator characteristics - It improves real throughput beyond algorithmic FLOP reductions alone.…
neural architecture
Hardware-Aware NAS is a neural architecture search approach that explicitly considers target hardware constraints — incorporating latency, energy consumption, memory usage…
neural architecture search
Hardware-aware NAS is architecture search that optimizes model structure under explicit hardware constraints such as latency memory and power - Search objectives combine task…
Hardware-Aware Neural Architecture Search Introduction & Motivation Hardware-Aware Neural Architecture Search addresses a central problem in automated design of nas architectures…
Hardware-Aware Neural Architecture Search (Extended Study) Introduction & Motivation Hardware-Aware Neural Architecture Search (Extended Study) addresses a central problem…
Hardware-Aware Neural Architecture Search (Extended Study) Introduction & Motivation Hardware-Aware Neural Architecture Search (Extended Study) addresses a central problem…
HDL, VHDL, Verilog, digital design, synthesis and simulation
A hardware description language is a specialized programming-like language used to describe the behavior and structure of digital circuits in text, so that designers can specify…
systemverilog vhdl, chisel hardware language, rtl abstraction, hdl synthesis
Register-transfer level (RTL) is the abstraction at which digital chips are designed. Rather than drawing individual transistors or gates, an engineer describes the circuit as…
hardware description language (hdl) simulation performance, hardware description language, description language (hdl), language (hdl) simulation, (hdl) simulation performance
Hardware Description Language (HDL) Simulation Performance Introduction & Motivation Hardware Description Language (HDL) Simulation Performance addresses a central problem…
palladium, veloce, zebu, emulation acceleration
Hardware Emulation is the use of specialized hardware platforms (FPGA arrays or custom processors) to execute RTL designs at speeds 100-10,000x faster than software simulation…
fpga prototyping asic, palladium zebu, hardware in the loop emulation, soc software bringup
Hardware Emulation and FPGA Prototyping represents the massive hardware-accelerated verification infrastructure that runs entirely unmanufactured, billion-gate system-on-chip…
fpga prototyping verification, palladium zebu emulator, pre silicon validation, emulation acceleration
Hardware Emulation and FPGA Prototyping are the pre-silicon verification platforms that map an SoC design onto reconfigurable hardware (emulators or FPGA boards) to achieve…