1,821 technical terms and definitions
dp-sgd, differentially private sgd, privacy
DP-SGD (Differentially Private Stochastic Gradient Descent) is the foundational algorithm for training machine learning models with formal differential privacy guarantees…
diffusion sampler, stable diffusion
DPM++ (Diffusion Probabilistic Model++) is an advanced sampling method for diffusion models — generating high-quality images in fewer steps than DDPM through improved ODE solvers…
generative models
DPM-Solver is a family of high-order ODE solvers specifically designed for the probability flow ODE of diffusion models, providing faster and more accurate sampling than generic…
generative models
DPM-Solver is the family of high-order numerical solvers for diffusion ODEs that attains strong quality with very few model evaluations - it is one of the most effective…
defects per million, quality metric
DPMO (Defects Per Million Opportunities) is the universal, normalized quality metric used across the global semiconductor, automotive, aerospace, and manufacturing industries…
dpmo, quality & reliability
DPMO is defects per million opportunities, a normalized metric expressing defect frequency relative to total opportunities - It enables cross-process comparison of quality…
direct preference, simpler
Direct Preference Optimization (DPO) is the fine-tuning algorithm that aligns language models with human preferences without requiring a separate reward model or reinforcement…
dpp, recommendation systems
DPP Rec is determinantal point process based recommendation for diversity-aware subset selection. - It models item-set probability so high-quality but mutually dissimilar items…
dppm, quality
DPPM (Defective Parts Per Million) is the primary quality metric measuring the rate of defective devices shipped to customers — calculated as , representing the outgoing quality…
dppm, yield enhancement
DPPM is defective parts per million, a quality metric that quantifies escaped defect rate in shipped units - DPPM normalizes field or outgoing defects by shipped volume to track…
dprnn, audio & speech
DPRNN is dual-path recurrent neural network tailored for efficient long-sequence speech separation - It applies stacked dual-path recurrent blocks to scale temporal modeling…
smartnic, smart nic, data processing unit, infrastructure offload, dpu infrastructure offload chip, nvidia bluefield 3 dpu, amd pensando, nvme over fabrics
A DPU, or data processing unit, also sold as a SmartNIC, is the third class of processor in a modern datacenter, sitting alongside the CPU and the GPU. Where the CPU runs…
dqn, reinforcement learning
DQN (Deep Q-Network) is the foundational deep reinforcement learning algorithm that combines Q-learning with deep neural networks — using a CNN to estimate the action-value…
DRAEM Discriminative Reconstruction Embedding for Defects Introduction & Motivation DRAEM Discriminative Reconstruction Embedding for Defects addresses a central problem…
optimization
Draft Model is the fast proposal model used in speculative decoding to generate candidate tokens - It is a core method in modern semiconductor AI serving…
inference
Draft model selection is the process of choosing the proposer model used in speculative decoding to maximize acceptance rate and net speedup under quality constraints - selection…
dragonfly algorithm navigation, dragonfly algorithm, algorithm navigation
Dragonfly Algorithm Navigation Introduction & Motivation Dragonfly Algorithm Navigation addresses a central problem in ml process control and path-quality-optimization prediction…
Dragonnet Targeted Regularization for CATE Estimation Introduction & Motivation Dragonnet Targeted Regularization for CATE Estimation addresses a central problem in causal…
drain-induced barrier lowering prediction, drain-induced barrier lowering, barrier lowering prediction, drain-induced barrier, barrier lowering, lowering prediction
Drain-Induced Barrier Lowering Prediction with Machine Learning Introduction & Motivation Drain-Induced Barrier Lowering Prediction with Machine Learning addresses a central…
drain-induced barrier lowering prediction, drain-induced barrier lowering, barrier lowering prediction, drain-induced barrier, barrier lowering, lowering prediction
Drain-Induced Barrier Lowering Prediction with Machine Learning Introduction & Motivation Drain-Induced Barrier Lowering Prediction with Machine Learning addresses a central…
ibm 1968 dennard sequential versus combinational device, 1t1c dram 1968 output depends on its own past state, dram memory 1968 first device this project built for persistence
Why Memory Needs an Entirely Different Structure Than Logic: The First Device This Project Has Built for Persistence, Not Speed 1. Why Every Earlier Series Built a Device That…
ibm dennard 1968 one transistor one capacitor memory cell, 1t1c dram charge storage replaces multi transistor latch, dram 1968 access transistor controls write and read
Store a Bit as Charge on a Capacitor, Not as a Latch of Transistors: Dennard's Radical Simplification 1. Replace a Circuit That Continuously Defends Its State with One Physical…
ibm dennard 1t1c word line bit line storage node transistor, 1t1c dram access mosfet selected row shared bit line, dram 1968 reuse silicon gate process for access transistor
Build the Access Transistor Using the Self-Aligned Gate Process Just Completed: A Direct Reuse of 1967's Silicon-Gate Process 1. The New Memory Architecture Does Not Require a New…
ibm dennard 1t1c mos capacitor stores bit charge, 1t1c dram capacitor area oxide thickness capacitance, dram 1968 mos capacitor becomes functional storage element
Build the Storage Capacitor Beside the Transistor: Turn the MOS Capacitor from a Test Structure into the Bit Itself 1. Reuse the Gate-Oxide-Silicon Stack for a Completely…
ibm dennard 1t1c subthreshold junction dielectric leakage, 1t1c dram storage node charge decay leakage current, dram 1968 dynamic memory leakage requires refresh
Confront Leakage: Why the Charge Does Not Stay Forever 1. The Same Off-State Current That Was Negligible for CMOS Logic Is Now the Central Failure Mechanism The 1963 CMOS series…
ibm dennard 1t1c write wait read retention test, 1t1c dram weakest cell retention distribution guard band, dram 1968 refresh interval protects stored charge margin
Measure the Retention Time and Set the Refresh Interval 1. Retention Time Is Measured from a Completed Write to the Last Reliable Read Step 5 established that leakage continuously…
ibm dennard 1t1c bit line charge sharing read, 1t1c dram sense amplify restore after every read, dram 1968 reading capacitor requires write back
Confront Destructive Readout: Reading the Cell Disturbs the Charge Being Read 1. The Bit Cannot Be Observed Without Connecting It to a Much Larger Electrical Node A 1T1C cell has…
ibm dennard 1t1c cell area compared with 6t memory, 1t1c dram repeated cell tile and shared periphery density, dram 1968 smaller cell enables higher bit density
Measure the Area Advantage Against a Six-Transistor Latch 1. Compare Repeated Cell Footprints, Not Transistor Counts in Isolation The density advantage of Dennard's cell comes…
ibm dennard 1t1c cell density shared array overhead, 1t1c dram refresh occupancy sensing restore tradeoff, dram 1968 qualify complete memory macro architecture
Qualify the Trade: Density Against Refresh Complexity 1. The Cell Becomes Simpler by Moving Work into the Array The 1T1C architecture does not eliminate the functions a memory…
ibm dennard 1t1c dynamic random access memory classification, 1t1c dram cell array macro release qualification, dram 1968 compact cell shared circuitry enables large memory
Classify and Release: The Architecture That Makes Large-Scale Memory Possible 1. Classify the Finished Device by What It Stores and What It Requires The completed one-transistor…
name dennard the actual 1968 ibm patent filing behind, name dennard the 1968 ibm patent filing
Name Dennard: The Actual 1968 IBM Patent Filing Behind This Series Every step in this series so far described the one-transistor, one-capacitor cell by its behavior; none named…
confront the sense amplifier choice open bit line versus, confront sense amplifier bit line topology choice
Confront the Sense-Amplifier Choice: Open Bit Line Versus Folded Bit Line Step 7 established that reading a 1T1C cell shares its charge onto a bit line and requires sensing…
confront the external refresh burden this cell creates before, confront the external refresh burden before automation
Confront the External Refresh Burden This Cell Creates, Before Any Chip Automates It Step 6 set a refresh interval as a cell-level timing requirement; at this series' own 1968…
ship the first commercial product intels 1103 1970, ship the intel 1103 first commercial product
Ship the First Commercial Product: Intel's 1103, 1970 The architecture this series built through Step 10 existed as IBM research and patent claims through 1968; it became…
compute the economics this architecture actually displaced cost per, compute cost per bit against magnetic core
Compute the Economics This Architecture Actually Displaced: Cost Per Bit Against Magnetic Core Step 8 measured area advantage in device terms; the commercial argument that…
establish how the industry actually licensed dennards 1968 claim, establish cross licensing around the 1968 patent
Establish How the Industry Actually Licensed Dennard's 1968 Claim A patented architecture that the patent-holder's own company does not exclusively commercialize (Step 14) raises…
model wafer scale yield for an array built from, model wafer scale yield for a repeated
Model Wafer-Scale Yield for an Array Built From One Repeated Cell Step 9 qualified density against refresh complexity at the architecture level; manufacturing this array at volume…
trace the discovery that would eventually threaten every shrinking, trace the alpha particle soft error discovery
Trace the Discovery That Would Eventually Threaten Every Shrinking Capacitor: Alpha-Particle Soft Errors This series' own chronology closes before this problem was identified, but…
distinguish what this series covers from what the later, distinguish this series from the 64k periphery
Distinguish What This Series Covers From What the Later Periphery Series Covers Three series in this project's DRAM lineage now exist; before closing this one, it is worth stating…
close this extension what dennards cell left for the, close the extension naming forward threads honestly
Close This Extension: What Dennard's Cell Left for the Rest of This Project to Inherit Ten additional steps have now deepened the attribution, economics, and limits of…
dram capacitor aspect ratio uniformity prediction, dram capacitor aspect, capacitor aspect ratio, aspect ratio uniformity, ratio uniformity prediction, aspect ratio
DRAM Capacitor Aspect Ratio Uniformity Prediction with Machine Learning Introduction & Motivation DRAM Capacitor Aspect Ratio Uniformity Prediction with Machine Learning addresses…
dram capacitor dielectric leakage current prediction, dram capacitor dielectric, capacitor dielectric leakage, dielectric leakage current, dram capacitor
DRAM Capacitor Dielectric Leakage Current Prediction with Machine Learning Introduction & Motivation DRAM Capacitor Dielectric Leakage Current Prediction with Machine Learning…
dram capacitor leakage drift prediction, dram capacitor leakage, capacitor leakage drift, leakage drift prediction, dram capacitor, capacitor leakage, leakage drift, drift prediction
DRAM Capacitor Leakage Drift Prediction with Machine Learning Introduction & Motivation DRAM Capacitor Leakage Drift Prediction with Machine Learning addresses a central problem…
M0C etch, deep contact DRAM, array to periphery contact, strap contact DRAM, high aspect ratio periphery contact
The deep MC contact — also called M0C or Deep Contact — has to etch all the way down through the entire height of the capacitor stack to reach the periphery transistors below it…
dram etch list, buried wordline etch, storage node hole etch, dram capacitor etch, dram process etch steps, 6f2 cell etch, bitline contact etch, mold dip out etch, hbm tsv etch
A modern 6F² buried-wordline DRAM cell runs through more than fifty named etch applications before a single bit can be stored, and nearly all of them exist to solve one problem…
dram cell structure, dram capacitor, dram refresh, 1t1c dram cell
DRAM (dynamic random-access memory) stores each bit as charge on a tiny capacitor, gated by a single access transistor — the '1T1C' cell. It is 'dynamic' because that charge leaks…
dram films
DRAM Film A DRAM film is a material layer used in the access transistor, storage capacitor or wiring of dynamic memory. Its role must be named: a capacitor dielectric and a gate…
dram film stack, dram film stacks
DRAM Filmstack A DRAM filmstack is an ordered set of layers belonging to a particular DRAM structure. There is no single stack covering the access transistor, capacitor, bit line…
dram front-end back-end integration, dram wafer to hbm packaging flow
DRAM front-end to back-end process integration is the single traveler that carries a bare silicon wafer through every module needed to make a working memory chip — cell…
DRAM Process A DRAM process is the coordinated set of fabrication modules that makes memory cells and their peripheral circuits. For conventional one-transistor/one-capacitor…