2,859 technical terms and definitions
shallow trench isolation DRAM, active area isolation, etch loading cell array, pad nitride strip, STI oxide recess
The cell STI etch cuts the shallow trench isolation that electrically separates one DRAM cell's active area from its neighbor, and inside the array this trench has to be narrower…
4k dram, dram4k 1973
Confront the 1K DRAM Density Wall The 1968 Dennard one-transistor, one-capacitor cell solved the structural problem of dense dynamic memory, and the parts that followed it through…
4k dram, dram4k 1973
Compare Pin Counts Before and After Multiplexing Without multiplexed addressing, a 4K-bit DRAM needing roughly twelve address bits would have required twelve dedicated address…
dram cost per bit, dram4k 1973
Compare TMS4030 Design Choices to the MK4096 The TMS4030 reached 4K density using TI's own cell and sense-amplifier design choices, which differed from Mostek's in process detail…
4k dram, dram4k 1973
Carry Lessons Forward to 16K and Beyond The engineering lesson of the 4K generation, that address-pin count had to be managed with multiplexing rather than simply adding more…
mostek mk4096, dram4k 1973
Close by Naming the 64K Generation as the Next Leap The 4K generation, anchored by Mostek's MK4096 and contested commercially by Texas Instruments' TMS4030, closed the gap between…
eprom eeprom history step 1 confront the problem dov frohman was actually solving at int, eprom eeprom history overview
Confront the Problem Dov Frohman Was Actually Solving at Intel 1. A Reliability Problem, Not a Memory Project In 1971, Dov Frohman was an engineer at Intel working on a question…
eprom eeprom history step 13 close the eprom eeprom history and hand off by name to nand, eprom eeprom history series close
Close the EPROM/EEPROM History and Hand Off, by Name, to NAND Flash 13. Closing This Series' Arc This series told a specific, previously-uncovered chapter of non-volatile memory…
selective etching, selective chemical etch, GAA channel release, sacrificial layer removal
Chemical etching. uses reaction chemistry chosen to remove a target material faster than adjacent masks, stop layers, channels, spacers, liners, or substrates. Selectivity is…
experimental mos bipolar logic step 1 why resistor transistor logic draws current in both states, rtl standing power baseline
Confront the 1962 Bipolar Logic Baseline: Why a Field-Effect Alternative Looked Worth the Risk 1. Why 1962's Digital Logic Was Entirely Bipolar, and Entirely Hungry for…
experimental mos bipolar logic step 4 why early mos devices had unpredictable threshold voltage, mos threshold voltage surface state charge
Characterize Threshold Voltage and Residual Surface-State Charge in the Early Oxide 1. Why the First Devices Worked but Did Not Behave Predictably Even with a passivated surface…
experimental mos bipolar logic step 5 positive oxide charge forced early pmos polarity choice, early pmos channel polarity choice
Confront Early PMOS Polarity: Why the First Working Devices Were P-Channel, Not N-Channel 1. Why Every Early Experimental MOS Device Used a P-Channel, Against the Intuitive Choice…
experimental mos bipolar logic step 7 half cv squared switching energy versus rtl standing power, mos switching energy versus rtl power
Compare MOS Gate-Capacitance Switching Energy Against Bipolar RTL Switching Energy 1. Why the Honest Energy Comparison Is Not as Favorable to MOS as It Later Became Switching…
experimental mos bipolar logic step 9 measured rtl noise margin falling with fan out count, rtl fan out noise margin limit
Confront RTLs Fan-Out and Noise-Margin Limits 1. Why RTL's Noise Margin Was the Family's Actual Practical Ceiling Measured across real RTL gates driving real fan-out loads…
experimental mos bipolar logic step 11 dtl delay cost versus early pmos gate delay and power, dtl delay versus early pmos gate delay
Compare DTL Propagation Delay and Power Against Early PMOS Gate Delay 1. Why DTL's Noise-Margin Fix Added Delay That Early PMOS Did Not Pay DTL's diode input network adds its own…
experimental mos bipolar logic step 13 mobile sodium ion migration under sustained gate bias, sodium ion mos threshold instability
Confront Early MOS Threshold Instability: Sodium-Ion Contamination and Oxide Drift 1. Why Devices That Worked on the Bench Failed Under Sustained Bias Devices that measured…
experimental mos bipolar logic step 16 mos off state leakage versus bipolar standing current, mos static power versus bipolar standby power
Compare Experimental MOS Static Power Against Bipolar Standby Power 1. Why Static Power, Not Switching Power, Was MOS's Clearest Measured Advantage Measuring a PMOS gate and…
experimental mos bipolar logic step 17 low mobility thick oxide and channel resistance slow early pmos, early pmos speed deficit versus bipolar
Confront the Experimental MOS Speed Deficit Against Bipolar Switching Speed 1. Why Early PMOS Could Not Yet Match Bipolar Switching Speed at Any Reasonable Voltage Measured…
experimental mos bipolar logic step 18 threshold scatter contamination and oxide pinhole defects limit yield, experimental mos yield production limit
Characterize Yield: Why Experimental MOS Struggled to Reach Production Volume 1. Why Laboratory Success Did Not Translate Directly Into a Shippable Product Line Across RCA's…
experimental mos bipolar logic step 20 honest split scoreboard mos density power versus bipolar speed yield, experimental mos bipolar logic series close
Close on Experimental MOS's 1962-1965 Arc: A Real Capability, Not Yet a Winning Product 1. Why This Series Ends on an Honest, Unresolved Competitive Standing, Not a Verdict By…
FIB cross section, focused ion beam milling, failure analysis imaging artifact, xenon plasma FIB, ion beam sputter rate
Curtaining is a milling artifact that shows up in a focused ion beam cross-section as a series of vertical streaks running straight through the image, caused by the ion beam…
first commercial mos linear ics step 10 overview, closing part a two threads mos density opened and the turn t
Closing Part A: Two Threads MOS Density Opened, and the Turn Toward Linear ICs 1. Two Named Threads Forward Part A closes here having covered the first commercial MOS integrated…
first commercial mos linear ics step 20 overview, closing the arc and handing off by name to cmos logics own c
Closing the Arc and Handing Off, by Name, to CMOS Logic's Own Commercial Era 1. What This Series Covered This series told two genuinely separate but contemporaneous commercial…
cloud ai, aws, azure, gcp, gpu cloud, managed ml
cloud computing is the on-demand delivery of compute, storage, networking, databases, platforms, and applications through pooled datacenter infrastructure. Cloud platforms are…
gpu kernel fusion optimization, operator fusion deep learning, kernel launch overhead, fused kernel computation, fusion compiler optimization
compiler optimization is the transformation of a correct program into semantically equivalent code that runs faster, uses less energy, occupies less memory, or maps efficiently…
grown junction 1951 check contacted element, current gain verification before encapsulation, diode only vs transistor action test, grown junction transistor functional test
Check the Contacted Element: Where the Placement Gamble Finally Resolves Step thirty's placement probability and step thirty-one's alloy-zone forgiveness were both framed in terms…
grown junction 1951 classify and mark, electrical grade binning acceptance region, production code permanent marking, grown junction transistor grading tiers
Classify and Mark: Subdividing the Region Final Test Only Accepted or Rejected Final test drew a single boundary around the acceptance region — everything inside passes…
grown junction 1951 cut rectangular bars, radial dopant non uniformity czochralski, rotational striae crystal growth, grown junction transistor bar to bar variation
Cut Rectangular Transistor Bars: Radial Non-Uniformity, Not Just Axial Every segregation and drift calculation this process has used so far — zone refining, the melt-concentration…
grown junction 1951 cut section containing junctions, junction margin saw damage measurement uncertainty, coarse cut n p n sandwich, grown junction transistor junction isolation cut
Cut a Section Containing Both Junctions: Margin Against What the Cut Itself Damages Step twenty-one located both junctions electrically, but "located" means "known within some…
grown junction crosswise slicing, grown junction transistor cut plane, diamond saw kerf loss ingot, grown junction transistor slicing angle
Crosswise Slicing: Cutting Perpendicular to Read Out the Grown Structure Every slice taken perpendicular to the pull axis, anywhere along the completed ingot's length, is…
cmos direct address readout, serial conveyor vs parallel grid, image sensor reference diagram
CCD's Walking Potential Well vs. CMOS's Direct Address two different answers to reading a million-point grid through a handful of pins Backside illumination later undid CMOS's one…
segregation dopant surface cap removal nitride oxide
Push an anneal hot enough to fully activate a shallow, high-dose implant, and a second problem shows up: the bare silicon surface starts losing dopant too — boron and phosphorus…
mask rom addressing step 14 close by naming how, close by naming
Close by Naming How This Series Completes the Mask-ROM Picture 1. Name What Each of the Three Series Actually Covers Three series now cover mask-programmed read-only memory on…
mask rom addressing step 4 contrast maskrom row select, contrast maskrom row
Contrast Mask-ROM Row Select Against DRAM RAS/CAS and SRAM Word-Line/Bit-Line, Architecturally 1. Line Up Three Addressing Shapes Side by Side Three memory technologies in this…
mask rom addressing step 5 count the real weeks, count the real
Count the Real Weeks a Photomask Set Took to Design and Fabricate 1. Separate Mask Design From Mask Fabrication A mask-ROM bit pattern was not something an engineer could change…
multi-feature exposure defocus window, iso-dense bias overlap, reticle error impact, process window intersection
An overlapping process window (also termed common process window) is the intersection of individual Exposure-Defocus (E-D) process windows across all critical feature types…
power mosfet igbt step 1 bipolar power transistor base drive second breakdown, bipolar power transistor base drive second breakdown
Confront the Bipolar Power Transistor's Base-Drive and Second-Breakdown Limits 1. Confront the Bipolar Power Transistor's Base-Drive and Second-Breakdown Limits By the early…
power mosfet igbt step 11 power mosfet high voltage on resistance limit, power mosfet high voltage on resistance limit
Confront the Power MOSFET's On-Resistance Wall Above a Few Hundred Volts 11. Confront the Power MOSFET's On-Resistance Wall Above a Few Hundred Volts…
power mosfet igbt step 18 igbt switching speed tail current bipolar comparison, igbt switching speed tail current bipolar comparison
Compare IGBT Switching Speed Against the Bipolar Transistor It Replaces 18. Compare IGBT Switching Speed Against the Bipolar Transistor It Replaces The IGBT switches slower than…
power mosfet igbt step 20 igbt gan sic wide bandgap power devices, igbt gan sic wide bandgap power devices
Close by Naming Where IGBT Sits Beside Emerging GaN and SiC Devices 20. Close by Naming Where IGBT Sits Beside Emerging GaN and SiC Devices This series has told the VDMOS-to-IGBT…
projection lithography, projection lithography 1973
Confront Contact Printing's Mask-Damage Problem The original 1957-era photolithography process pressed the mask directly against the photoresist-coated wafer during exposure…
perkin elmer micralign, projection lithography 1973
Close by Naming the Modern Exposure Lineage Without Retelling This series has covered the 1973 shift from contact printing to projection alignment and exposure, anchored…
dual damascene, copper interconnect, damascene process flow, barrier seed layer, copper cmp
Copper dual damascene interconnect architectures, electrochemical superfilling, and barrier-seed metallization constitute the back-end-of-line (BEOL) wiring systems that route…
shared memory, cache, scratchpad
Cache memory is a small, fast storage hierarchy placed near compute units to keep recently used instructions and data from repeatedly traveling to slower, more energy-intensive…
nanosheet release etch inner spacer, gaafet sige selective etch, suspended nanosheet stiction
SiGe Selective Etch and Nanosheet Channel Release A gate-all-around transistor gets its name from the gate wrapping completely around the channel on all four sides, but…
sram six transistor step 1 confront the refresh free requirement, sram refresh free static storage
Confront the Refresh-Free Requirement DRAM's 1T1C Cell Could Not Satisfy 1. Confront the Refresh-Free Requirement DRAM's 1T1C Cell Could Not Satisfy Dynamic RAM's…
sram six transistor step 3 six transistor cell topology, six transistor sram cell topology
Count the Six Transistors: Four for the Latch, Two for Access 3. Count the Six Transistors: Four for the Latch, Two for Access The cross-coupled pair from Step 2 is a complete…
sram six transistor step 7 speed advantage no refresh, sram speed advantage over dram
Compare SRAM's Speed Advantage: No Refresh, No Destructive Readout 7. Compare SRAM's Speed Advantage: No Refresh, No Destructive Readout SRAM is faster than DRAM for reasons that…
sram six transistor step 13 bit line capacitance sense margin, sram bit line capacitance sense margin
Confront Bit-Line Capacitance and Sense-Margin at Small Geometries 13. Confront Bit-Line Capacitance and Sense-Margin at Small Geometries The same shrinkage that tightens…
sram six transistor step 19 sram leakage wall finfet, sram leakage wall deep submicron finfet
Confront SRAM's Own Leakage Wall in the Deep-Submicron and FinFET Eras 19. Confront SRAM's Own Leakage Wall in the Deep-Submicron and FinFET Eras The static-power concern named…