wire load model

Wire Load Model (WLM) is a statistical model of interconnect wire length and RC parasitics based on net fanout — used during synthesis and pre-layout STA to estimate delay before actual routing completes.

Why Wire Load Models?

  • During synthesis: No physical routing exists — cannot compute actual wire length/delay.
  • Need parasitic estimate for timing closure decisions.
  • WLM: Table of estimated wire length as a function of fanout, derived from similar designs.

WLM Structure

WIRE_LOAD "wlm_typical_10K" {
  RESISTANCE  0.00010 ;
  CAPACITANCE 0.000110 ;
  AREA        0.003 ;
  SLOPE       0.040 ;
  FANOUT_LENGTH  1  0.050 ;
  FANOUT_LENGTH  2  0.100 ;
  FANOUT_LENGTH  4  0.200 ;
  FANOUT_LENGTH  8  0.400 ;
  FANOUT_LENGTH 16  0.800 ;
}
  • `FANOUT_LENGTH`: Estimated wire length (μm) for given fanout.
  • R and C per unit length from technology LEF or Liberty file.
  • Net delay: $R_{wire} \times C_{wire}$ added to cell output delay.

WLM Limitations

  • Accuracy: ±50% of actual post-route delay (statistical average).
  • High-fanout nets: WLM underestimates — clock buffers, reset trees.
  • Hierarchical blocks: Different WLM for each hierarchy level.
  • Modern flows: Many designs bypass WLM entirely, using prototype routing for better estimates.

Zero Wire Load

  • Special case: All wire delays = 0.
  • Used for: Technology exploration, behavioral synthesis, first-pass area estimation.
  • Not used for final timing sign-off.

Post-Route vs. WLM

  • WLM-based synthesis: Close timing at ±50% accuracy.
  • Post-route STA: Refine closure with actual extracted parasitics.
  • Gap between WLM and actual: 10–30% timing difference common.

Virtual Flat WLM

  • Most conservative: Assumes net can be routed anywhere in the die.
  • Most accurate pre-layout for flat designs.
  • Less suitable for hierarchical block-level synthesis.

Wire load models are the timing estimation bridge between synthesis and physical implementation — while they lack precision, they prevent synthesis from optimizing away critical-path cells that will be needed once routing reveals actual wire lengths.

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