semiconductor memory sram dram

The 1T1C DRAM cell: one bit as charge on a tiny capacitorA single transistor gates charge onto a capacitor — dense and cheap, but it leaks and must be refreshed1 · One transistor, one capthe simplest memory cell there isWL (wordline)BLaccess FETC (storage)charged = 1, empty = 0the cap is a deep trench or tall stackThe wordline turns on the transistor,connecting the bitline to the capacitorso charge can flow in or out.2 · Write, read, refreshreading destroys the bitWriteraise WL, drive BL high or low; the capcharges to that level, then WL closes.Read (destructive)precharge BL to mid-level, raise WL; thecap nudges BL up or down by a few mV.A sense amp resolves it — and mustwrite the value back, since the read drained it.Refreshthe cap leaks in milliseconds, so everyrow is read and rewritten thousands oftimes a second. That refresh traffic andits power is the price of DRAM density.3 · Dense, cheap, volatilethe opposite tradeoff to SRAMTiny cell = huge capacityone FET + one cap packs far more bitsper mm² than SRAM’s six transistors.Slower than SRAMsensing tiny charge takes time; DRAM ismain memory, not the on-die cache.Scaling the capacitorit must stay big enough to sense even ascells shrink — hence deep 3D structures.The capacitor is the challengeTo hold enough charge in a shrinkingfootprint, makers build tall stacked ordeep trench caps with high-k dielectrics.This, not the transistor, gates DRAM scaling.Charge = the bitA full capacitor is a 1, an emptyone is a 0 — stored as electrons.Volatile & refreshedLeaks in milliseconds; every row isrewritten constantly to survive.Density over speedThe opposite of SRAM — smaller andcheaper per bit, but slower & volatile.

Semiconductor Memory Technologies are the diverse family of integrated circuit storage devices — from volatile SRAM and DRAM that lose data when power is removed, to non-volatile Flash and emerging memories that retain data indefinitely — each optimized for different combinations of speed, density, endurance, and cost that define the memory hierarchy from processor cache to mass storage.

SRAM (Static RAM):
- 6T Bitcell: two cross-coupled inverters form bistable latch, two access transistors connect to bitlines — data retained as long as power is applied; no refresh required; read by sensing differential voltage on complementary bitlines
- Performance: fastest memory technology — access time 0.5-2 ns; used for L1/L2/L3 caches where speed is critical; operates at full processor clock frequency
- Area Penalty: 6T cell is 100-150× larger than DRAM cell — typical bitcell area: 0.02-0.05 μm² at 7nm node; limits practical SRAM capacity to tens of megabytes on-chip
- Design Challenges: read stability (noise margin), write ability, and hold margin must be simultaneously optimized — cell ratio (pull-down/access transistor ratio) and pull-up ratio determine read/write margins; process variation in minimum-size transistors limits yield

DRAM (Dynamic RAM):
- 1T1C Cell: single access transistor and storage capacitor — charge on capacitor represents stored bit; capacitor charge leaks through transistor sub-threshold current requiring periodic refresh (every 32-64 ms)
- Capacitor Scaling: maintaining >20 fF capacitance as cells shrink below 20 nm pitch — high-k dielectrics (ZrO₂/Al₂O₃/HfO₂ stack), 3D capacitor structures (pillar or cylinder) with aspect ratios >60:1
- Refresh Overhead: each row must be periodically read and rewritten — refresh consumes 10-30% of DRAM bandwidth and power; Row Hammer vulnerability: repeated access to one row disturbs adjacent rows requiring mitigation (TRR, PARA)
- HBM (High Bandwidth Memory): 3D-stacked DRAM with TSVs providing >1 TB/s bandwidth — 4-16 die stack with wide (1024-bit) interface; bonded to logic die or silicon interposer; essential for AI accelerators

Non-Volatile Memory:
- NAND Flash: floating gate or charge trap transistors store data as threshold voltage levels — SLC (1 bit/cell), MLC (2), TLC (3), QLC (4 bits/cell); 3D NAND stacks 100-300 layers vertically for density; program/erase endurance 1K-100K cycles depending on technology
- NOR Flash: random-access read capability at near-DRAM speed — used for code storage (boot ROM) in embedded systems; lower density than NAND but enables execute-in-place (XIP) operation
- MRAM (Magnetoresistive RAM): magnetic tunnel junction stores data as parallel/anti-parallel magnetization — non-volatile, unlimited endurance, SRAM-comparable speed; becoming embedded replacement for SRAM/Flash in MCUs
- ReRAM/PCRAM: resistive switching (filament formation/dissolution) or phase change (crystalline/amorphous) — positioned between DRAM and Flash in the memory hierarchy; Intel Optane used PCRAM before discontinuation

Semiconductor memory technologies collectively form the multi-level memory hierarchy that bridges the enormous speed gap between processors and storage — understanding the fundamental tradeoffs between speed, density, volatility, endurance, and cost is essential for system architects designing the memory subsystems of modern computing platforms.

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