passivation layer

Passivation Layer — the final protective coating deposited over the completed chip to shield it from moisture, contamination, mechanical damage, and corrosion during packaging and operation.

Structure

• Typical stack: SiO₂ (500nm) + Si₃N₄ (500–1000nm)
• Sometimes: SiON or polyimide added for additional protection
• Openings etched over bond pads for wire bonding or bump connections

Why Passivation Is Critical

• Moisture barrier: Water + ions cause corrosion of aluminum/copper wires and shifts in transistor parameters
• Mechanical protection: Guards against scratches during handling and dicing
• Ion barrier: Sodium (Na⁺) and other mobile ions shift threshold voltages
• Scratch protection: Die surface survives wafer probe needle marks

Materials

• Silicon Nitride (Si₃N₄): Excellent moisture barrier. Deposited by PECVD at 300–400°C
• Silicon Dioxide (SiO₂): Stress buffer between chip surface and hard nitride
• Polyimide: Soft, thick stress buffer for flip-chip applications

Pad Opening

• After passivation deposition, lithography + etch removes passivation over bond pads
• Care needed: Over-etch can damage pad metal; under-etch leaves residue preventing bonding

Passivation is the last fabrication step before the wafer leaves the fab — it's the chip's armor that must survive decades of operation in harsh environments.