off state leakage Ioff
Off-State Leakage Current (I_off) Control addresses the management of drain current that flows when the transistor is nominally in the off state (V_GS < V_th), comprising subthreshold diffusion current, gate-induced drain leakage (GIDL), and gate oxide tunneling — collectively responsible for standby power that now consumes 30-50% of total chip power at advanced technology nodes.
I_off Components:
| Component | Mechanism | Dependence | Relative Magnitude |
|---|---|---|---|
| Subthreshold leakage | Diffusion over source-channel barrier | Exponential in V_th | Dominant at low V_th |
| GIDL | Band-to-band tunneling at drain | Exponential in V_DG | Dominant at high V_th |
| Gate oxide tunneling | Quantum tunneling through gate dielectric | Exponential in EOT | Reduced by high-k |
| Junction leakage | Reverse-biased S/D diode | Moderate | Usually smallest |
The V_th - I_off Tradeoff: Subthreshold leakage scales as I_sub ∝ exp(-V_th / (n·kT/q)), where n is the ideality factor (~1.1-1.3) and kT/q ≈ 26mV at room temperature. Each ~70mV reduction in V_th increases I_off by ~10×. This creates the fundamental performance-power tradeoff: lower V_th → faster switching but higher leakage.
Multi-Threshold Voltage Design: Modern processes offer 3-5 V_th options:
| Flavor | V_th (typical) | I_off | Speed | Use Case |
|---|---|---|---|---|
| uLVT | ~150mV | Highest | Fastest | Critical timing paths |
| LVT | ~250mV | High | Fast | Performance paths |
| SVT/RVT | ~350mV | Medium | Moderate | Default |
| HVT | ~450mV | Low | Slower | Non-critical paths |
| uHVT | ~550mV | Lowest | Slowest | Always-on domains |
Design tools automatically select V_th flavors per transistor to meet timing with minimum leakage power.
Process Techniques for I_off Control: Channel doping (higher doping → higher V_th, but increased RDF variability); gate work function metal (primary V_th knob at advanced nodes); body bias (forward bias lowers V_th for speed, reverse bias raises V_th for power); fin width/sheet thickness (thinner body → better electrostatic control → lower DIBL → lower I_off at same V_th); and channel material (high-mobility materials like SiGe channel for PMOS enable higher V_th with good drive current).
Circuit-Level Leakage Management: Power gating — completely disconnect power to idle blocks using header/footer sleep transistors (eliminates leakage in gated blocks); body biasing — apply reverse body bias in standby to increase V_th dynamically; state retention — use high-V_th cells to hold state while power-gating the rest; MTCMOS — mix high-V_th (low leakage) and low-V_th (high performance) transistors in the same design.
Off-state leakage control has become the central challenge of CMOS power management — where the exponential sensitivity of subthreshold current to threshold voltage forces an intricate co-optimization of process technology, transistor design, and circuit architecture to deliver usable performance within the power constraints of modern computing systems.