memory redundancy
# Memory Redundancy and Row/Column Repair
A memory array the size of a modern DRAM or NAND die will always have some defective bit cells — the array is simply too large for a 100%-defect-free yield to be realistic at any process node. Memory redundancy is the architectural answer: build a handful of extra spare rows and columns into the array on purpose, and give the chip the ability to permanently reroute any address that maps to a defective cell onto one of those spares instead, turning what would otherwise be a dead, unsellable die into a fully functional part.
The repair itself is a permanent, one-time remapping decision made at test, not something the chip figures out on its own at runtime. Wafer-level test exercises every bit in the array and builds a defect map identifying exactly which rows and columns contain failing cells. A repair algorithm then solves an allocation problem against that defect map — deciding which of the limited spare rows and columns to assign to which defective addresses, since a single spare row can only cover defects that happen to share that row, and the chip only has so many spares to work with. Once that allocation is computed, it gets permanently encoded into the chip's own repair fuses (commonly eFuse or laser-trim elements, the same irreversible-programming mechanisms covered elsewhere in this session) — baking the remapping decision into the silicon itself rather than leaving it as something firmware decides each time the chip powers up.
The economics only work because the spare-row/column overhead is small relative to the yield it recovers, and that tradeoff gets tuned per product generation. Adding spare rows and columns costs real die area — area that produces no additional usable capacity in a perfect die, pure overhead on every single part shipped. But without redundancy, a single defective bit anywhere in a multi-gigabit array would kill the entire die, and at advanced nodes with real defect densities, that would make large memory arrays essentially unmanufacturable at viable yield. Architects size the spare-row and spare-column count against the process's known defect density and the array's own size — more spares recover more yield but cost more area, and the optimum shifts with every process generation as defect density and array size both change.
Built-in self-repair (BISR) extends this same idea to run automatically inside the chip itself, using on-chip memory BIST to find defects and an on-chip repair algorithm to fix them without ever leaving the tester. Rather than relying entirely on external test equipment to find defects and compute the repair solution, a BISR-equipped memory array runs its own self-test at power-on or during a dedicated test mode, identifies failing addresses internally, and programs its own repair fuses directly — reducing dependence on expensive external test time and making repair possible even after the part has left the factory, such as during an in-field diagnostic or burn-in screen that surfaces a defect the original factory test missed.
eFuse and Zener zap trim (575) both permanently encode a correction after manufacturing — one bit, one irreversible physical change at a time. Memory redundancy is the same underlying concept applied at the architectural scale of an entire defective row or column instead of a single analog trim bit, which is exactly why the repair fuses storing that remap use the same melted-link or broken-junction physics this session's other entries already cover.