hmos 1978 measure clock speed payoff against original nmos

# Step 7 — Measure the Clock-Speed Payoff Against the Original NMOS Generation

## 1. The Quantitative Balance Sheet: Was the HMOS Redesign Worth It?

By evaluating clock speed, power-delay product, and transistor density directly against standard 1974 NMOS, we quantify the exact return on investment bought by HMOS’s fabrication complexity. In Steps 1 through 6, we tracked the comprehensive process overhaul that created Intel HMOS: decoupling depletion load thresholds via ion implantation, sizing aspect ratios without serpentine waste, thinning the gate oxide to $70\ \text{nm}$, shunting polysilicon interconnects with polycide, and adding a second polysilicon layer ($+3$ masks). Every step added capital tool expense and process risk.

To evaluate whether this redesign justified its manufacturing overhead, we compare the quantitative figures of merit across three generational milestones:
1. Standard 1974 NMOS (Intel 8080A Baseline): $6\ \mu\text{m}$ lithography, $t_{\text{ox}} = 100\ \text{nm}$, single-poly, non-implanted load.
2. 1978 HMOS-I (Intel 8086 / 2147 SRAM): $3.5\ \mu\text{m}$ lithography, $t_{\text{ox}} = 70\ \text{nm}$, double-poly, dual ion implant.
3. 1979 HMOS-II (Intel 8086-2 / 2147H): $2.0\ \mu\text{m}$ lithography, $t_{\text{ox}} = 40\ \text{nm}$, scaled double-poly.

The fundamental engineering metric governing digital logic efficiency is the Power-Delay Product (PDP):

$$\text{PDP} = P_{\text{gate}} \cdot \tau_{\text{gate}} \approx (V_{dd} I_{\text{avg}}) \cdot \tau_{\text{gate}}$$

While supply voltage remained anchored at $V_{dd} = 5.0\ \text{V}$ for TTL compatibility, the gate delay dropped by $4\times$ from $4.0\ \text{ns}$ to $1.0\ \text{ns}$. Because drive current was tuned via thin oxide rather than raw power consumption, the power-delay product dropped four-fold from $4.0\ \text{pJ}$ down to $1.0\ \text{pJ}$.

Quantitative Payoff Ledger: 1974 NMOS vs. HMOS measuring clock frequency, power-delay product, and transistor density gains 1974 STANDARD NMOS Channel Length (L): 6.0 µm Gate Delay (τ): 4.0 – 12.0 ns CPU Clock Speed: 2.0 MHz (8080A) Power-Delay (PDP): 4.0 pJ SRAM Access: 250 ns (2102A) Density: 220 trans/mm² 1978 HMOS-I (INTEL 8086) Channel Length (L): 3.5 µm (−42%) Gate Delay (τ): 1.0 ns (4× Faster) CPU Clock Speed: 5.0 – 8.0 MHz (4×) Power-Delay (PDP): 1.0 pJ (4× Gain) SRAM Access: 55 ns (2147) Density: 880 trans/mm² (4×) 1979 HMOS-II (SCALED) Channel Length (L): 2.0 µm (−67%) Gate Delay (τ): 0.4 ns (10× Faster) CPU Clock Speed: 10.0 MHz (8086-1) Power-Delay (PDP): 0.48 pJ (8× Gain) SRAM Access: 35 ns (2147H) Density: 1,800 trans/mm² (8×) THE FINAL INDUSTRIAL VERDICT ✓ 4× Clock Frequency Increase: Microprocessor clocks jumped from 2 MHz to 8 MHz while retaining 5V TTL compatibility ✓ 8× Density Multiplier: Made it commercially feasible to place 29,000 transistors on a single 33 mm² silicon die The +50% mask-count overhead was repaid tenfold in raw computational throughput and commercial dominance.

## 2. The Power-Delay Frontier: Energy Efficiency Across Generations

Mapping gate delay against power dissipation demonstrates how HMOS shifted the fundamental energy-efficiency frontier of silicon logic.

The Power-Delay Frontier: 1974 Baseline to HMOS-II hyperbolic power-delay contours (PDP) showing orders-of-magnitude energy efficiency improvements POWER VS. DELAY CONTOURS Delay τ (ns) Power P (mW) PDP = 4.0 pJ PDP = 1.0 pJ PDP = 0.5 pJ 8080A (1974) 8085A (1976) 8086 (1978 HMOS) HMOS-II (1979) The Energy Miracle of HMOS: • Transistors switched 4× faster without drawing more power per gate ✓ 8086 ran at 8 MHz inside the same 40-pin DIP package thermal envelope (1.5W) REAL-WORLD PRODUCTS Intel 2147 4K Static RAM: • Replaced 1K bipolar ECL memories • Access time: 55 ns (vs. 250 ns 2102) ✓ 4× denser, 5× faster, auto-powerdown Became mainframe cache standard. Intel 8086 Microprocessor: • 29,000 transistors on 33 mm² die • Clock rate: 5 MHz → 8 MHz → 10 MHz ✓ Outperformed 8080 by > 10× Selected by IBM for the 1981 IBM PC, launching the modern x86 era. The Milestone Significance: HMOS proved that co-engineering the load, oxide, and interconnect could deliver bipolar ECL speeds at MOS density and power, crowning NMOS as the semiconductor industry's flagship technology.

## 3. Place This Step in the Project's Own Lineage

Step 7 provides the quantitative validation for the entire HMOS engineering overhaul:
1. The Culmination of the Redesign: Steps 2 through 6 added ion implantation, precision aspect ratios, 70 nm gate oxides, polycide shunts, and double polysilicon layers. Step 7 compiles the performance receipts: measuring the $4\times$ clock jump ($2\ \text{MHz} \to 8\ \text{MHz}$), the $4\times$ power-delay reduction ($4\ \text{pJ} \to 1\ \text{pJ}$), and the $4\times$ density multiplier that enabled the 29,000-transistor Intel 8086.
2. The Economic Rationale Proven: Just as Step 9 of the 1974 DRAM series proved that 3D trench and stacked capacitors justified their $+40\%$ wafer cost premium, Step 7 proves that double-poly HMOS repaid its $+50\%$ lithography overhead by delivering mainframe cache speeds (2147 SRAM) and birthing the PC microprocessor market.
3. Approaching the Limits of the Paradigm: But success brought new danger. In Step 8, we follow Intel's attempt to push this fixed-voltage NMOS architecture into its second generation (HMOS-II, $L = 2.0\ \mu\text{m}$), confronting the violent re-emergence of the $E = V/L$ field constraint and the ultimate thermodynamic wall that paved the way for CMOS.

Go deeper with CFSGPT

Get AI-powered deep-dives, save terms, and run advanced simulations — free account.

Create Free Account