finfet 2010s redesign standard cell libraries around fin quantized track height

# FinFET (2010s): Step 10 — Redesign Standard-Cell Libraries Around Fin-Quantized Track Heights

## 1. A Layout Constraint Fin Quantization Forces

Step 9 established that a FinFET's drive current is fixed by its fin count rather than by a continuously drawn width. Because every transistor on a standard-cell row must fit within the same cell height, and cell height is itself set by how many fins can physically fit side by side within it, fin-count quantization reaches directly into standard-cell library layout in a way planar width scaling never did.

## 2. Cell Height as a Fin-Counting Problem

Standard-cell height is conventionally expressed in routing tracks; a FinFET-era cell's height is effectively the number of fins its tallest transistor needs, spaced at the fin pitch Step 6 established, plus margin for isolation and contacts. Library architects choose a fixed cell height — commonly expressed as 6-track, 7.5-track, or similar conventions — and every standard cell in the library must fit its required fin counts for both NMOS and PMOS within that shared height.

## 3. The Tradeoff Library-Wide Cell Height Choice Creates

A taller fixed cell height admits more fins per transistor, supporting higher drive-current cells at the cost of lower transistor density per unit area; a shorter fixed cell height packs cells more densely but caps the maximum fin count, and therefore the maximum drive current, any single cell in the library can offer. This is a library-wide decision made once for an entire process node, not a per-cell choice, because every cell must share the same track height to abut cleanly in a row.

## 4. What This Step Does and Does Not Cover

This step covers standard-cell logic libraries specifically; SRAM bit-cells face a related but distinct version of this same fin-counting constraint, covered separately in Step 15, after source/drain and parasitic-capacitance topics specific to the fin geometry are addressed in Steps 11-14.

Cell Track Height Trades Drive Current Headroom for Density maximum usable fin count per transistor and achievable cell density, plotted against chosen standard-cell track height maximum fin count a cell's tallest transistor can use (rises with taller fixed track height) achievable transistor density per unit area (falls as track height is made taller) a library picks one track height for the whole node — it cannot vary cell by cell process generation advances left to right across this chart fin pitch from Step 6 sets how many fins actually fit within a given track height 6-track, 7.5-track, and similar conventions are this tradeoff made explicit library-wide
Cell Height, Reframed as a Fin-Counting Budget why a FinFET-era library's track-height choice is really a decision about maximum fin count FIN PITCH (Step 6) Bulk Silicon Substrate P_fin Contacted Fin Pitch sets how many fins physically fit side by side within any given cell height TRACK HEIGHT CHOICE Bulk Silicon Substrate H_fin W_fin < 10nm · AR > 4:1 6-track, 7.5-track, etc. — chosen once, shared by every cell in the library MAX DRIVE PER CELL Bulk Silicon Substrate PU (1-Fin) PD (2-Fin) Quantized Ratio β=2 the ceiling on fin count, and therefore drive current, every cell in the library inherits Key Semiconductor Engineering Takeaway SRAM bit-cells face a related but distinct version of this same constraint, covered in Step 15

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