euv-double-patterning

Two patterning operations for a dense target layer. EUV double patterning uses more than one EUV-defined patterning operation to create a final layout that cannot be manufactured satisfactorily in a single exposure flow. One common approach decomposes features between separate masks and transfers the complementary patterns through successive processing steps. EUV is the exposure technology; double patterning describes how the intended pattern is split and integrated.

Resolution and process margin motivate decomposition. As pitches shrink, a single exposure can encounter limits in imaging contrast, stochastic defects, resist behavior, and the ability to transfer small features reliably. Splitting a dense target into less demanding component patterns can improve individual exposures. The final structure must still satisfy electrical dimensions and spacing. Merely exposing the same mask twice is not equivalent to decomposing a layout into two distinct patterns.

Overlay becomes part of the final geometry. When neighboring features originate from different masks, relative placement error can alter their spacing or connectivity. Etch bias, critical-dimension variation, and mask errors also accumulate through the sequence. Layout decomposition must avoid incompatible feature relationships and can introduce additional design restrictions. A process that resolves each component separately can still fail when the combined pattern is evaluated electrically.

High-NA single patterning is a different option. Imec has demonstrated dense logic and memory patterns with single-exposure 0.55NA EUV and discusses its ability to replace selected multiple-patterning flows. This does not establish one universal crossover point. Pitch, feature type, resist, defects, and tool economics affect the choice. Both optical capability and complete process integration matter when comparing High-NA single exposure with lower-NA multiple patterning.

Count the entire manufacturing sequence. A comparison should include masks, exposures, deposition, etching, cleaning, metrology, rework risk, cycle time, and yield. Multiple patterning can extend an existing scanner platform while increasing process complexity. High-NA can simplify some sequences while introducing its own equipment and integration costs. The useful decision is the lowest-cost reliable implementation of a specific layer, rather than the shortest description of its lithography.

Sources and further reading. [Imec High-NA single-patterning demonstrations](https://www.imec-int.com/en/press/imec-demonstrates-logic-and-dram-structures-using-high-na-euv-lithography); [IEEE Electron Devices Society July 2024](https://www.ieee.org/ns/periodicals/EDS/EDS-JULY-2024-HTML-v1/InnerFiles/LandPage.html).

Read EUV double patterning as a layer-specific extension of EUV patterning that trades simpler component patterns for integration complexity.