what is an etch spacer process iep endpoint algorithm

An etch spacer process Interferometric Endpoint algorithm (etch spacer process IEP endpoint algorithm) is a precision nanometer-scale optical phase tracking and interface-reflection monitoring system engineered to govern anisotropic spacer formation in advanced CMOS and 3D memory architectures. During the fabrication of self-aligned contacts, FinFET gate sidewalls, and gate-all-around (GAA) nanosheets, a conformal low-$k$ dielectric liner (typically 5 nm to 15 nm of $Si_3N_4, SiBCN, SiOCN,$ or $SiO_2$) is deposited over gate topography and subsequently etched anisotropically with fluorocarbon or hydrofluorocarbon plasmas ($CH_3F/O_2, CH_2F_2/Ar, CF_4$). The goal of the spacer etch is to completely clear the horizontal dielectric film from the silicon substrate (source/drain landing pads) and gate hardmask caps while retaining the vertical sidewall spacer with zero silicon loss. Because a conformal spacer layer is ultra-thin ($<15\text{ nm}$), it does not generate multiple sinusoidal Fabry-Pérot interference fringes. Instead, a spacer IEP endpoint algorithm tracks sub-fringe optical phase evolution, instantaneous reflectance slope ($dR/dt$), and terminal destructive interference minima on a dedicated scribe-line planar macro or array grating, triggering an atomic-scale soft-landing handoff before halogen ions recess underlying active silicon. At a high level, how an IEP endpoint algorithm governs spacer etching looks like this:

Conformal spacer deposition
ALD SiN / SiBCN / SiOCN (8-15nm) over 3D gate fin
Normal-incidence laser launch
Polarized 405nm / 670nm beam on planar scribe macro
Spacer IEP sub-fringe tracking loopSub-quarter-wave phase tracking and interface slope lock
Initial reflectance plateau
High R from ALD film atop crystalline silicon
Sub-fringe monotonic drop
Thinning from 12nm down to sub-5nm zone
First derivative minimum (dR/dt)
Maximum clearing velocity inflection point
Terminal destructive minimum lock
Phase touchdown alert at d_rem = 2.0 nm
↻ per-sample phase tracking
Selective soft-landing switch
Low-bias CH3F/O2/He polymer-rich over-etch
Pristine source/drain preservation
Complete horizontal clearing with <0.3nm Si recess

A few principles are essential for understanding how spacer IEP endpoint algorithms operate, why sub-fringe phase detection replaces multi-cycle fringe counting, and how short optical wavelengths resolve ultra-thin dielectric films:

The sub-fringe optical regime of ultra-thin spacers. In conventional dielectric etching, film thicknesses are hundreds of nanometers thick, producing multiple periodic Fabry-Pérot interference peaks and valleys ($\Delta d = \lambda_0 / (2n)$). In modern FinFET and GAA spacer etching, however, the horizontal film thickness is only $d_0 \approx 8\text{ to }15\text{ nm}$. For a typical silicon nitride spacer ($n_{SiN} \approx 2.02$) illuminated by a standard $\lambda_0 = 670\text{ nm}$ laser diode:

$$\text{Full Fringe Cycle } \Delta d = \frac{670\text{ nm}}{2 \times 2.02} \approx 165.8\text{ nm} \quad \implies \quad \text{Quarter-Wave Thickness } \frac{\lambda_0}{4n} \approx 82.9\text{ nm}$$

Because the total physical thickness of the spacer ($10\text{ nm}$) is less than one-eighth of a single optical wavelength ($\sim 12\%$ of a fringe cycle), the IEP algorithm cannot count peaks. Instead, it operates entirely within the *fractional sub-fringe regime*, tracking the monotonic decrease in reflectance $R(t)$ toward the terminal substrate boundary:

$$R(t) = \frac{r_1^2 + r_2^2 + 2r_1r_2 \cos(2\delta(t))}{1 + r_1^2 r_2^2 + 2r_1r_2 \cos(2\delta(t))} \quad \text{where } \delta(t) = \frac{2\pi n_{\text{spacer}} d(t)}{\lambda_0}$$

Wavelength optimization for sub-10nm thickness sensitivity. Sensitivity to thickness changes is proportional to the optical phase gradient:

$$\frac{\partial R}{\partial d} \propto \frac{n_{\text{spacer}}}{\lambda_0} \sin\left(\frac{4\pi n_{\text{spacer}} d}{\lambda_0}\right)$$

To maximize $\partial R / \partial d$ in the ultra-thin $d < 10\text{ nm}$ regime, advanced spacer IEP systems employ short-wavelength ultraviolet and violet laser diodes (e.g., $\lambda_0 = 405\text{ nm}$ or $375\text{ nm}$) rather than standard infrared beams. At $\lambda_0 = 405\text{ nm}$, the phase sensitivity is over $65\%$ higher than at 670 nm, converting a 1.0 nm change in spacer thickness into an easily measurable $2.4\%$ change in normalized reflectance.

Spacer Etch IEP Sub-Fringe Endpoint Dynamics conformal 3D profile clearance, 405nm optical phase slope, and source/drain recess protection 3D Gate & Sidewall Spacer Silicon Substrate (Source/Drain) < 0.3 nm Recess Tolerance Poly / Metal Gate Fin SiN Cap Spacer Spacer Clearing Clearing Sub-Fringe Reflectance R(t) & Slope Trigger Main Anisotropic Etch Over-Etch (Low Bias) TOUCHDOWN TRIGGER (2nm Rem) Max Negative Slope dR/dt Horizontal SiN (12nm) Bare Si Landing Plateau Process Time (s) → Reflectance Sub-Fringe Phase Tracking Fractional 12% cycle sensitivity Violet 405nm Optics +65% phase slope resolution Zero Si Recess Lock Preserves source/drain junction spacer IEP algorithms track monotonic sub-fringe phase slope rather than counting periodic sinusoidal cycles sub-nanometer touchdown detection commands the low-bias over-etch before energetic fluorocarbon ions recess silicon

First-derivative inflection ($dR/dt$) and curvature tracking. Because the spacer etch does not produce periodic oscillations, the IEP algorithm evaluates continuous derivatives of reflectance:
1. *Steady Etch Rate Plateau:* In the bulk phase ($d > 5\text{ nm}$), reflectance falls at a stable rate ($dR/dt \approx \text{const}$).
2. *Inflection Point Minimum:* As the film thins past 3.0 nm and areas of bare silicon begin to emerge, $|dR/dt|$ reaches its maximum absolute value ($d^2R/dt^2 = 0$).
3. *Touchdown Alert:* When the second derivative $d^2R/dt^2$ flips positive and reflectance flattens toward the substrate bare-silicon reflectance baseline ($R_{\text{Si}}$), the algorithm flags remaining thickness $d_{\text{rem}} \approx 2.0\text{ nm}$. This triggers an instantaneous recipe interrupt: RF substrate bias is lowered from 120 V to <30 V, and the feedgas is shifted to a polymerizing $CH_3F/O_2/He$ mixture. This over-etch step has $>50:1$ selectivity of $Si_3N_4$ over silicon, clearing footing residues while restricting silicon substrate recess to less than 0.3 nm (less than two atomic monolayers).

Grating scatterometry and 3D profile co-optimization. In advanced nanosheet architectures, planar scribe-line test pads can etch up to 15% faster than high-density 3D transistor arrays due to micro-loading and reactive ion etch (RIE) lag. To overcome this discrepancy, state-of-the-art spacer IEP systems direct a polarized spot onto a periodic array grating mimicking active FinFET pitches (e.g., 30 nm pitch). By measuring specular reflectance alongside zero-order diffraction polarization changes, the algorithm models both vertical clearance and vertical sidewall CD erosion simultaneously, ensuring pristine gate integrity across high-density SRAM and open logic regions alike.

Read a spacer etch process IEP endpoint algorithm through an *atomic-altimeter* lens: navigating without the luxury of repeating periodic landmarks, it measures the sheer steepness of the optical descent to land a high-energy plasma feather-softly onto silicon source and drain junctions without causing atomic gouging.

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