ESD Protection

ESD protection clamp design co-optimizes trigger voltage and holding voltage together, since the two parameters interact rather than behaving as independent dials a designer can tune separately. A clamp triggered too close to the chip's normal operating voltage risks nuisance triggering during ordinary power-supply noise; a holding voltage set too close to that same operating voltage risks the clamp staying latched on after a transient rather than returning cleanly to its off state once the discharge event ends, both failure modes bounded by the same underlying ESD design window, which is why trigger and holding voltage are treated as a coupled pair during clamp sizing rather than tuned in isolation.