DIBL drain induced barrier lowering
Drain-Induced Barrier Lowering (DIBL) is the short-channel effect where the drain voltage reduces the source-channel potential barrier, causing the threshold voltage to decrease with increasing drain bias — quantified in mV/V and serving as a primary metric for electrostatic integrity of the transistor channel, with DIBL directly determining the distinction between "on" and "off" states in scaled transistors.
Physical Mechanism: In a long-channel MOSFET, the potential barrier between source and channel is controlled solely by the gate voltage. In a short-channel device, the drain depletion region extends close enough to the source that the drain voltage also influences the barrier height. Higher V_DS lowers the source-channel barrier, allowing more carriers to flow even below the nominal threshold voltage.
DIBL Quantification: DIBL = -(V_th,low_VDS - V_th,high_VDS) / (V_DS,high - V_DS,low) in mV/V. For example, if V_th at V_DS = 0.05V is 300mV and V_th at V_DS = 0.75V is 270mV: DIBL = -(300 - 270) / (0.75 - 0.05) = 43 mV/V.
DIBL Targets by Generation:
| Technology | DIBL Target | Channel Control |
|---|---|---|
| Planar bulk (90nm) | <100 mV/V | Channel doping, halo |
| Planar bulk (28nm) | <80 mV/V | Heavy halo, retrograde well |
| FinFET (14nm) | <30 mV/V | Thin fin, 3-sided gate |
| FinFET (5nm) | <20 mV/V | Thinner fin, taller |
| GAA nanosheet (3nm) | <15 mV/V | 4-sided gate control |
Impact on Circuit Design: DIBL causes the transistor I_off to increase when the drain is at V_DD (which is the normal operating condition for the "off" transistor in CMOS logic). This means static leakage power is higher than V_th measurements at low V_DS would suggest. For SRAM, DIBL degrades the static noise margin because the access transistor's effective V_th drops under the bit-line voltage, weakening the stored data.
DIBL Mitigation Approaches:
| Approach | Mechanism | Limitation |
|---|---|---|
| Halo implant | Increase channel doping near S/D | Increases RDF |
| SOI (thin body) | Eliminate deep S/D depletion | Cost, floating body |
| FinFET | Narrow fin, 3-sided gate | Fin width quantization |
| GAA/nanosheet | 4-sided gate wrapping | Process complexity |
| Undoped channel | Fully depleted, gate WF control | Work function tuning |
| Reduced channel length variation | Tighter gate CD | Lithography cost |
DIBL vs. Other Short-Channel Effects: DIBL is closely related to but distinct from: V_th roll-off (V_th decreases with shorter gate length even at low V_DS, due to charge sharing); punchthrough (the extreme case where S/D depletion regions merge and gate loses control entirely); and subthreshold slope degradation (the on/off transition becomes less steep as DIBL increases, approaching the 60mV/dec thermal limit from above).
DIBL serves as the essential figure of merit for transistor electrostatic integrity — a single number that captures how effectively the gate controls the channel against drain interference, and whose progressive reduction from >100 mV/V in planar to <15 mV/V in GAA architectures traces the history of transistor scaling innovation.