copper damascene

Copper dual-damascene: you can’t etch copper, so carve the mold and fill itEtch trench and via into the dielectric, line and fill with copper, then polish the overflow away1 · Etch the moldvia + trench in one dielectriclow-k dielectricmetal below (Mn)trench (the wire)viavia drops to the layer beneath“Dual” = both the via down to the layerbelow and the trench that becomes thewire are etched into one dielectric, thenfilled together — fewer steps than doingvia and wire separately.2 · Line, seed, fill, polishbarrier keeps copper containedbarrierCuoverburden → CMP removesA thin barrier (TaN/Ta) lines the walls socopper can’t diffuse into the dielectric; aseed layer starts electroplating, whichfills trench and via void-free. CMP thenpolishes the overfill back to the dielectric.3 · Why this waycopper is faster but stubbornCopper beats aluminumlower resistance and better electromigration— faster, more reliable interconnect.But copper won’t etchit forms no volatile etch byproduct, soyou can’t pattern it like aluminum.So invert the processpattern the dielectric instead and fill thegaps — the damascene inlay approach.Stacked layer on layerA modern chip stacks 10–20 metal levelsthis way, each a dual-damascene layer.Barrier and low-k scaling — keeping boththin — is the hard part at each new node.Carve, don’t etchPattern the dielectric and inlay copper —because copper itself can’t be etched.Barrier + fill + CMPLine the walls, electroplate void-free,polish the overburden away.Dual = via + trenchOne fill makes both the vertical via andthe horizontal wire — fewer steps.

Copper damascene is the dominant interconnect fabrication method using copper metal fill in damascene-patterned dielectric trenches and vias. Why copper: Cu resistivity (1.7 uOhm-cm) is ~40% lower than Al (2.7 uOhm-cm). Better electromigration resistance. Enables faster, more reliable interconnects. Cu challenge: Cannot be dry-etched by conventional RIE. Must use damascene (inlaid) approach. Diffuses rapidly in Si and SiO2, requiring barriers. Process sequence: Etch dielectric features, PVD TaN/Ta barrier, PVD Cu seed, electroplate Cu fill, Cu CMP (multi-step), post-CMP clean, cap layer deposition. Electroplating: Bottom-up fill using electrochemical deposition with accelerator/suppressor/leveler additives. Superfill provides void-free filling of high-AR features. Barrier: TaN provides diffusion barrier, Ta provides Cu adhesion and promotes (111) texture for electromigration resistance. CMP: Multi-step - bulk Cu removal, barrier removal, buff. Slurry chemistry with BTA inhibitor controls dishing. Cap layer: SiCN or SiN capping layer over Cu prevents oxidation and Cu diffusion into next dielectric level. Also serves as etch stop. Electromigration: Cu has higher EM resistance than Al. Bamboo grain structure and proper interfaces extend EM lifetime. Adoption: First production use by IBM at 220nm node (1997). Now universal for interconnect.

Go deeper with CFSGPT

Get AI-powered deep-dives, save terms, and run advanced simulations — free account.

Create Free Account