clearwater-forest

Clearwater Forest is Intel’s codename for the Xeon 6+ E-core server processor family. It combines Intel 18A compute tiles with active base tiles, separate I/O dies and advanced packaging to increase useful throughput within a server’s power and space limits. Intel’s current product listings identify launched configurations rather than only a future roadmap. The architectural idea is to place dense compute above the fabric and memory-related functions that feed it.

Define the service
Parallel workload
Requests, VMs or packet flows
Service target
Throughput and tail latency
Map the server
Compute and memory
Cores, cache, DDR5 and NUMA
Power and cooling
Sustained operating envelope
Validate the deployment
Realistic traffic
Contention and scaling
Count useful work
Energy and cost per service

E-core density is a workload choice. Clearwater Forest uses Darkmont efficient cores and scales to configurations with up to 288 cores per socket. Its intended applications include cloud-native services, parallel scale-out workloads and telecommunications infrastructure. Those uses can benefit from many independently runnable tasks, but the core count alone does not establish service capacity. Serialization, memory access patterns, operating-system overhead and shared-resource contention still determine how much work a server completes at the required response time.

The physical partition is central to the design. Intel’s architecture deck depicts twelve Intel 18A compute tiles, three Intel 3-family active base tiles, two Intel 7 I/O tiles and twelve EMIB bridges. Earlier Intel process material identifies the base technology more specifically as Intel 3-T. This is a heterogeneous manufacturing strategy: different functions use different process families within one package. The active base is useful silicon containing cache, fabric and memory functions, rather than merely a passive mechanical support for the compute dies.

Clearwater Forest: Compute Above an Active Base Xeon 6+ · vertical compute-to-base links meet lateral package interconnects Active base Intel 3 family Active base Intel 3 family Active base Intel 3 family I/O tile Intel 7 I/O tile Intel 7 12 compute tiles Intel 18A / Darkmont Up to 288 E-cores per socket Foveros Direct 3D Cu-to-Cu hybrid bonds Three active base tiles: cache, fabric and memory functions EMIB: lateral bridges connect package regions Two I/O tiles peripheral and system links Functional topology only: placement, die dimensions and bridge symbols are schematic. Intel 18A identifies the compute dies; the active base uses a different process family.

Vertical bonding and lateral bridging solve different connection problems. Foveros Direct 3D joins compute tiles to active base tiles through dense copper-to-copper hybrid connections. EMIB provides short lateral interconnects between package regions. Combining the two allows many smaller dies to operate as one processor package. Connection density and short routes can help data movement, but assembly still requires alignment control, interface quality, test access and thermal planning. Good individual dies do not guarantee a good assembled package.

Intel 18A applies to the compute tier. RibbonFET gate-all-around transistors and PowerVia backside power delivery are features of the Intel 18A compute process. The first changes device electrostatics; the second changes how supply current reaches the devices and how routing resources are allocated. Neither makes the separately manufactured base or I/O tiles into Intel 18A dies. Likewise, the presence of an active base and Foveros Direct does not establish that the product uses the separately defined Intel 18A-PT platform.

The memory system must feed the cores. Intel describes twelve DDR5 channels and configurations supporting data rates up to 8000 MT/s. At that rate, twelve channels carrying eight data bytes per transfer have a theoretical aggregate data rate of 768 GB/s. That arithmetic excludes the effects of access patterns, refresh, command overhead and contention; it is not sustained application bandwidth. DIMM population, supported module characteristics, cache locality and software placement influence the bandwidth actually delivered to each service.

More Cores Still Share a Memory System Core density helps only when memory, software and the power envelope keep up Up to 288 E-cores — symbolic clusters, not individual core placement 12 DDR5 channels; populated DIMMs and supported speed depend on the platform. Rate example: 12 × 8 bytes × 8000 MT/s = 768 GB/s theoretical data bandwidth.

A launched processor still needs a specific system comparison. Intel’s product catalog lists the Xeon 6990E+ with a Q2 2026 launch, 288 cores, 576 MB of cache and a 450 W TDP. Other listed models have different core counts, cache and power specifications. TDP is a processor specification, rather than the measured wall power of a complete server. Compare the exact SKU, memory setup, software, cooling and utilization using completed requests or jobs at a stated latency target. An earlier preview’s availability target should not replace the current product listing.

Sources and further reading. [Intel Xeon 6+ platform and specifications](https://www.intel.com/content/www/us/en/products/details/processors/xeon/6-plus-series.html); [Intel catalog: products formerly Clearwater Forest](https://www.intel.com/content/www/us/en/ark/products/codename/236204/products-formerly-clearwater-forest.html); [Intel Xeon 6+ architecture deck](https://cdrdv2-public.intel.com/866623/xeon-6-plus-product-deck.pdf); [Intel’s active-base and process explanation](https://www.intel.com/content/www/us/en/newsroom/news/kevin-obuckley-talks-progress-intel-18a.html).

Read Clearwater Forest as a stacked throughput system: many efficient cores are useful when the active base, memory, package, software and cooling can sustain the service those cores are meant to deliver.

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