channel-release-etch

Channel release etch is the selective removal of sacrificial material around semiconductor channel sheets so that a gate can later surround them. In a common silicon/silicon-germanium nanosheet flow, SiGe is removed while the silicon sheets remain connected to source and drain. The process must clear the gate cavity while preserving channel thickness, surface quality, nearby dielectrics and vulnerable source/drain material. Its success depends on the complete structure and material history as well as the etch chemistry.

Release opens the future gate region. In a replacement-gate nanosheet process, the dummy gate is removed to provide access to the channel stack. Selective etching then removes sacrificial layers from that region, leaving separated sheets supported by their source/drain connections. Gate dielectric and metal are added afterward. This differs from the earlier inner-spacer recess, which creates limited lateral pockets near the stack ends. The main illustration is a transverse section: the source/drain anchors lie outside the page, so the released sheets appear separated in this view.

Selectivity measures a rate contrast under stated conditions. For a specified material pair, etch selectivity is commonly expressed as the target-material removal rate divided by the protected-material removal rate. High SiGe-to-Si selectivity helps preserve silicon, but a single ratio cannot establish complete release, smooth surfaces or protection of every exposed dielectric. IBM’s IEDM 2019 research connects reduced silicon thinning with improved device behavior. A 2024 NF3-based study also distinguishes cyclic and direct etching, illustrating that etch rate and selectivity must be evaluated together within the selected process.

Different widths create different clearing and exposure histories. Where etchants access a sacrificial layer from its sides, a wider stack presents a longer lateral path to its center. Structures that clear earlier may continue exposing their silicon while the slowest region is still being released. Seoul National University’s 2020 study analyzes width-dependent thinning and resulting electrical effects using physical characterization and device simulation. The compact diagram shows one equal-penetration example; actual removal rates and the required overetch margin also depend on access geometry, composition and process conditions.

Earlier processing changes the material being etched. Epitaxial composition, sheet spacing and previous heat treatments influence the interfaces presented to the release module. In a 2026 experimental study, researchers examined how nanosheet geometry and annealing affected selective removal, including germanium interdiffusion and etch behavior. Such results make the thermal history part of process development, rather than an unrelated upstream detail. Parameters measured on a blanket film or one test structure need confirmation on the integrated stack and its range of device geometries.

The source/drain and inner-spacer barrier need protection. Release chemistry can reach vulnerable source/drain epitaxy through inadequate coverage or paths around an inner spacer. IBM’s 2023 work investigates spacer profile, length, protective buffers and etch chemistry as coupled ways to mitigate that damage. Longer exposure therefore has consequences beyond clearing the final residual core. A qualified process checks channel preservation, spacer integrity and source/drain retention together. Wet, thermal-gas, plasma-assisted and cyclic approaches have different integration requirements; the term channel release does not identify one universal recipe.

A cleared cavity still needs physical and electrical verification. Cross-sectional imaging and composition analysis can investigate residual sacrificial material, channel thickness, gap dimensions and damage. Surface condition and structural integrity also matter because subsequent dielectric deposition and gate fill use the newly exposed interfaces. Electrical measurements then examine leakage, threshold-voltage distributions, drive current and reliability, with circuit loading determining the timing impact. A credible release process connects those results across the supported geometry range, rather than treating a nominal etch time or one attractive micrograph as sufficient qualification.

Sources and further reading. [IBM IEDM 2019: selective SiGe etching and silicon preservation](https://research.ibm.com/publications/a-novel-dry-selective-etch-of-sige-for-the-enablement-of-high-performance-logic-stacked-gate-all-around-nanosheet-devices); [2024 experimental study of NF3-based selective etching](https://pubmed.ncbi.nlm.nih.gov/38869553/); [Seoul National University: width-dependent channel-release effects](https://snu.elsevierpure.com/en/publications/investigation-of-electrical-characteristic-behavior-induced-by-ch/); [2026 study of structure and thermal-budget effects](https://pmc.ncbi.nlm.nih.gov/articles/PMC13304493/); [IBM SSDM 2023: source/drain damage mitigation](https://research.ibm.com/publications/epi-sourcedrain-damage-mitigation-with-inner-spacer-and-buffer-optimization-in-stacked-nanosheet-gate-all-around-transistors).

Read channel release etch as a selective-removal and preservation problem: clear the intended cavity, retain the useful channels and surrounding structures, then demonstrate that the completed transistor performs reliably.